Lead Physical Design Engineer
Nxp · Pune
- Experience8–10 yrs
- SalaryNot disclosed
- Work modeonsite
- Levelexecutive
- Posted10 Sept 2026
About Nxp
Nxp is hiring in Pune in semiconductors electronics. This role looks for around 8+ years of experience.
Skills
- ASIC physical design
- Floorplanning
- Power grid design
- Placement optimization
- Clock Tree Synthesis
- Routing
- MCMM timing closure
- Static timing analysis
- DRC/LVS
- IR drop analysis
- Electromigration
- Signal integrity
- Physical ECOs
- Scripting
The role
A physical design engineer works in semiconductor VLSI engineering. They implement advanced SoC and IP blocks from synthesized netlists to GDSII using floorplanning, power grid design, placement, clock tree synthesis, routing, and timing closure across MCMM scenarios. Their defining skills are ASIC physical design, clock tree synthesis, and timing closure, alongside DRC/LVS signoff, IR drop analysis, electromigration compliance, signal integrity, physical ECOs, and scripting automation.
Full job description
We are seeking a highly skilled and experienced Physical Design Engineer with strong fundamentals in physical design implementation to join our growing VLSI team. In this role, you will contribute to the implementation and signoff of complex SoC/IP blocks in advanced technology nodes, ensuring high-quality delivery aligned with NXP’s stringent PPA (Power, Performance, Area) and reliability standards.
Key Responsibilities
Execute block & Chip level physical design from synthesized netlist to GDSII:
Floorplanning and power grid design
Placement and optimization
Clock Tree Synthesis (CTS)
Routing and post-route optimization
Drive timing convergence across MCMM scenarios in collaboration with STA teams
Ensure design closure including:
Setup/hold timing closure
DRC/LVS clean signoff
IR drop and electromigration (EM) compliance
Debug and resolve:
Congestion issues
SI/crosstalk problems
Functional and physical ECOs
Collaborate cross-functionally with:
RTL/design teams to improve QoR
DFT teams for test readiness
Packaging and full-chip integration teams
Contribute to methodology improvements and automation through scripting
Follow and enforce NXP design methodologies, quality and reliability standards
Required Qualifications
Bachelor’s/Master’s degree in Electronics / Electrical Engineering / Microelectronics
8 - 10 years of experience in ASIC Physical Design
More information about NXP in India...
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