Senior Physical Design Engineer

NXP Semiconductors · Pune Division

  • Experience8–10 yrs
  • SalaryNot disclosed
  • Work modehybrid
  • Levelexecutive
  • Posted18 Sept 2026
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About NXP Semiconductors

NXP Semiconductors is hiring in Pune Division in semiconductors electronics. This role looks for around 8+ years of experience.

Skills

  • Floorplanning
  • Power Planning
  • Placement Optimization
  • Clock Tree Synthesis
  • Routing
  • Timing Closure
  • Physical Verification
  • Static Timing Analysis
  • Multi-Mode Multi-Corner
  • Crosstalk Analysis
  • Signal Integrity Analysis
  • ECO Flows
  • Timing Signoff
  • Physical Signoff
  • IR Drop Analysis
  • Electromigration Analysis
  • DRC/LVS Closure
  • Reliability Checks
  • Cadence Innovus
  • Synopsys ICC2
  • PrimeTime
  • Tempus
  • RedHawk
  • Voltus
  • StarRC
  • Quantus
  • Calibre

The role

A physical design engineer in semiconductor manufacturing delivers complex SoC and IP blocks from netlist to GDSII using floorplanning, clock tree synthesis, and timing closure. They optimize power, performance, and area across process corners, resolve signal integrity and reliability issues, and automate physical implementation and signoff flows. Their skills include floorplanning, clock tree synthesis, timing closure, physical verification, static timing analysis, multi-mode multi-corner methodology, ECO flows, and EDA tools.

Full job description

Job Title: Senior Physical Design Engineer

Location

Pune / Bangalore / Hyderabad (Hybrid)

Experience

8-10 Years

Job Summary

We are seeking a highly motivated and experienced Senior Physical Design Engineer to join our VLSI Physical Design team. The candidate will be responsible for delivering high-quality physical implementation of complex SoC/IP blocks from netlist to GDSII, ensuring timing, power, area, and reliability targets are met. The ideal candidate should have hands-on expertise in advanced node design implementation and signoff methodologies.

Key Responsibilities

Own end-to-end physical design implementation of complex digital blocks/subsystems.Drive floorplanning, power planning, placement, CTS, routing, timing closure, and physical verification.Perform design optimization for PPA (Power, Performance, Area) targets.Execute timing closure across multiple operating modes and process corners.Analyze and resolve setup, hold, SI, IR-drop, EM, and congestion issues.Collaborate with RTL, Synthesis, DFT, STA, Package, and Signoff teams to achieve project milestones.Support ECO implementation and tapeout activities.Develop and enhance PD methodologies, automation flows, and scripts to improve productivity.Review design quality and mentor junior engineers.Work closely with global cross-functional teams.

Required Technical Skills

Strong expertise in:FloorplanningPower PlanningPlacement OptimizationClock Tree Synthesis (CTS)RoutingTiming ClosurePhysical Verification

STA & Signoff

In-depth knowledge of:Static Timing Analysis (STA)Multi-Mode Multi-Corner (MMMC) methodologiesCrosstalk/SI AnalysisECO FlowsTiming Signoff

Physical Signoff

Experience with:IR Drop AnalysisElectromigration (EM) AnalysisDRC/LVS ClosureReliability Checks

Tools

Hands-on Experience With Industry-standard EDA Tools

Cadence InnovusSynopsys ICC2PrimeTimeTempusRedHawk / VoltusStarRC / QuantusCalibre

Educational Qualification

Bachelor's or Master's Degree in Electronics, VLSI, Electrical Engineering, or related field.

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