Lead Physical Design Engineer
NXP Semiconductors · Pune Division
- Experience8–10 yrs
- SalaryNot disclosed
- Work modeunknown
- Levelexecutive
- Posted18 Sept 2026
About NXP Semiconductors
NXP Semiconductors is hiring in Pune Division in semiconductors electronics. This role looks for around 8+ years of experience.
Skills
- ASIC Physical Design
- GDSII
- Floorplanning
- Clock Tree Synthesis
- MCMM
- Static Timing Analysis
- DRC/LVS
- Signal Integrity
- Power Integrity
- Electromigration
- Scripting
- Microelectronics
The role
A physical design engineer in semiconductor manufacturing implements complex SoC and IP blocks from synthesized netlists through GDSII, using floorplanning, power grid design, placement, clock tree synthesis, routing, and signoff for advanced technology nodes. They drive MCMM timing convergence and design closure while resolving congestion, signal integrity, and physical ECO issues. Their skills include ASIC physical design, clock tree synthesis, and GDSII implementation, alongside floorplanning, power integrity, electromigration, DRC/LVS, scripting, and microelectronics.
Full job description
We are seeking a highly skilled and experienced Physical Design Engineer with strong fundamentals in physical design implementation to join our growing VLSI team. In this role, you will contribute to the implementation and signoff of complex SoC/IP blocks in advanced technology nodes, ensuring high-quality delivery aligned with NXP’s stringent PPA (Power, Performance, Area) and reliability standards.
Key Responsibilities
Execute block & Chip level physical design from synthesized netlist to GDSII:Floorplanning and power grid designPlacement and optimizationClock Tree Synthesis (CTS)Routing and post-route optimizationDrive timing convergence across MCMM scenarios in collaboration with STA teamsEnsure design closure including:Setup/hold timing closureDRC/LVS clean signoffIR drop and electromigration (EM) complianceDebug and resolve:Congestion issuesSI/crosstalk problemsFunctional and physical ECOsCollaborate cross-functionally with:RTL/design teams to improve QoRDFT teams for test readinessPackaging and full-chip integration teamsContribute to methodology improvements and automation through scriptingFollow and enforce NXP design methodologies, quality and reliability standards
Required Qualifications
Bachelor’s/Master’s degree in Electronics / Electrical Engineering / Microelectronics8 - 10 years of experience in ASIC Physical Design
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