DFT Engineer - Pune
N Human Resources & Management Systems · Mumbai City
- Experience5–9 yrs
- SalaryNot disclosed
- Work modeonsite
- Posted29 Sept 2026
About N Human Resources & Management Systems
N Human Resources & Management Systems is hiring in Mumbai City in media advertising. This role looks for around 5+ years of experience.
Skills
- ATPG
- scan insertion
- fault coverage analysis
- MBIST/LBIST
- JTAG
- IEEE 1149.1
- DFT-aware constraints
- scan chain stitching
- test compression
- test point insertion
- silicon debug
- Tessent
- DFTMAX
The role
A DFT engineer at a VLSI delivery company designs test architecture and implementation using ATPG, scan testing, and MBIST/LBIST, taking designs from RTL through tapeout. The role also applies JTAG and Tessent for testability closure and silicon debug.
Full job description
N Human Resources & Management Systems | Full time
We are hiring a DFT Engineer to join our VLSI delivery team. You will own design-for-test architecture and implementation across design blocks, ensuring strong fault coverage and manufacturing test readiness from RTL through tapeout.
Key Responsibilities:Scan insertion, ATPG pattern generation, and fault coverage analysisMBIST/LBIST architecture definition and implementation for memory and logic testBoundary scan (JTAG/IEEE 1149.1) and DFT-aware constraint developmentScan chain stitching, compression, and test point insertionDebug of silicon test failures and correlation with simulation resultsLead and mentor a team of 3-4 engineers on DFT methodology and flowsPartner closely with RTL design, Physical Design, and STA teams on testability closureRequirements:5+ years of hands-on experience in DFT (ATPG, scan, MBIST/LBIST)Strong knowledge of Tessent/DFTMAX or similar industry-standard DFT toolsComprehensive understanding of test coverage, pattern generation, and silicon debug .