FPGA Design Engineer - Vivado Expert
Mercor · India
- Experience2–5 yrs
- SalaryDisclosed
- Work moderemote
- Levelmid
- Posted13 Sept 2026
About Mercor
Mercor is hiring in India in technology software. This role looks for around 2+ years of experience.
Skills
- Vivado
- FPGA
- RTL
- Microsoft Windows
The role
A design verification engineer at a technology research marketplace develops and verifies FPGA and RTL designs using Vivado, evaluates digital hardware design functionality, and analyzes high-resolution screenshots.
Full job description
About The Job
Mercor connects elite creative and technical talent with leading AI research labs. Headquartered in San Francisco, our investors include Benchmark, General Catalyst, Peter Thiel, Adam D'Angelo, Larry Summers, and Jack Dorsey.
Position: Application Users - Vivado on Windows - STEM
Type: Contract
Compensation: $45–$55/hour
Location: Remote
Role Responsibilities
Evaluate the functionality of Vivado on Windows for FPGA and Digital Hardware Design.Develop and verify FPGA and RTL designs using Vivado.Capture and analyze screenshots with more than 2.5 megapixels using either a high-resolution monitor or a dual-monitor setup.Work independently to ensure timely completion of tasks without the provision of software licenses or hardware.Collaborate asynchronously with teams to improve design and verification processes.
Qualifications
Must-Have
Experience with Vivado on Windows.Ability to capture screenshots with more than 2.5 megapixels.Access to a PC running Windows with Vivado installed.
Application Process (Takes 20–30 mins to complete)
Upload resumeAI interview based on your resumeSubmit form
Resources & Support
For details about the interview process and platform information, please check: https://talent.docs.mercor.com/welcomeFor any help or support, reach out to: support@mercor.com
PS: Our team reviews applications daily. Please complete your AI interview and application steps to be considered for this opportunity.
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