Technical Staff Engineer - Verification

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Job Description:

About the Role

We are seeking an experienced Ethernet Protocol Verification Engineer to develop and execute verification strategies for Ethernet MAC, PCS and PHY for our next generation of FPGA. In this role, you will define verification specifications, develop comprehensive verification plans, and drive hands-on simulation-based functional verification using industry-standard methodologies such as System Verilog and UVM. You will independently manage challenging verification activities, debug RTL against design intent, and collaborate closely with cross-functional teams to ensure successful project outcomes. Hands-on project experience with leading-edge verification methodologies such as OVM/UVM is required.

This role requires strong expertise in Ethernet standard, packet-based verification, and hardware/software debug skill

This role also includes mentoring engineers, sharing best practices, and contributing to a culture of technical excellence, innovation, and continuous improvement.

Requirements/Qualifications:

Bachelor’s or Master’s degree in Electrical Engineering or a related field.

Required Skills and Experience

12+ years of functional verification experience, with strong hands-on verification expertise in Ethernet 40G/100G, 1588 PTP, JESD204 simulation verification.

Strong protocol knowledge of Ethernet and AMBA AXI/AHB protocols.

Strong scripting skills in Python, Shell, Perl, and TCL.

Experience with coverage-driven and assertion-based verification methodologies.

Experience developing constrained-random and directed simulation testcases using System Verilog/UVM; knowledge of C-based testcase development is a plus.

Solid understanding of IC chip design, development flows, and verification methodologies.

Proficiency in HDL languages, including System Verilog, Verilog, and VHDL.

Proven ability to develop verification plans, build robust UVM testbenches, define functional coverage models, execute regressions, analyze coverage gaps, and drive closure against verification goals.

Travel Time:

0% - 25%

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