Staff/Principal Functional Verification Engineer (Memory Subsystem)
Advanced Micro Devices (AMD) · Hyderabad
- Experience12–17 yrs
- SalaryNot disclosed
- Work modeonsite
- Posted23 Sept 2026
About Advanced Micro Devices (AMD)
Advanced Micro Devices (AMD) is hiring in Hyderabad in semiconductors electronics. This role looks for around 12+ years of experience.
Skills
- UVM
- OVM
- Verilog
- SystemVerilog
- Synopsys VCS
- Cadence IES
- memory controller protocols
- UCIe
- DDR5
- DDR6
- RLD3
- HBM
- DDR
- LPDDR
- assertion-based verification
- metric-driven verification
- regression management
- database management
The role
A design verification engineer at a semiconductor product company develops UVM, SystemVerilog, and formal verification environments for memory controllers and high-speed interfaces, applying memory controller protocols and simulation tools to validate high-performance IP and SoC designs. The role also uses assertion-based verification and silicon debug.
Full job description
Job Summary
SMTS Engineer to provide technical leadership and contribution on high speed interface Verification. The individual will help design, develop and use simulation and/or formal based verification environments, at block and Sun-System level, to prove the functional correctness of UCIe, DDR5/6 RLD3 Memory Controllee Designs.
The ideal candidate is one who has a proven track record on driving strategies and successful verification execution high performance IPs and/or SOC designs.
Responsibilities
SMTS Engineer to provide technical leadership and contribution on high speed interface Verification.
The individual will help design, develop and use simulation and/or formal based verification environments, at block and Sun-System level, to prove the functional correctness of UCIe, DDR5/6 RLD3 Memory Controller Designs.
Require hands on experience with verification of state of the art memory controllers such as HBM, DDR, LPDDR, UCIe.
Requires strong understanding of current memory controller protocols and calibration board skew and jitter modeling.
With a proven track record in technical leadership of teams. This includes planning, execution, tracking, verification closure, and delivery to programs.
Candidate is expected to be a strong team player with good communication and leadership skills and one who is able to positively and strategically influence the Memory Controller design teams with an eye towards improving overall product quality.
Qualifications
BS with 12+ years or MS with 11+ years or PhD with 9+ years in Electrical Engineering, Computer Engineering or Computer Science.
Experience with development of UVM/OVM and/or Verilog, SystemVerilog test benches and usage of simulation tools/debug environments such as Synopsys VCS, Cadence IES to verify memory controller IPs.
Proven track record on driving strategies and successful verification execution on Memory Controllers high performance IPs and/or SOC designs.
Proven track record in technical leadership of teams of 9+ engineers. This includes planning, execution, tracking, verification closure, and delivery to programs.
Hands on experience with verification of high speed interface like UCIe is a plus.
Strong understanding of state of the art of verification techniques, including assertion and metric-driven verification. Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high performance IP and/or VLSI designs is a plus.
Familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management.
Experience with formal property checking tools such as Cadence, Jasper and Synopsys is a plus.
Experience with gate level simulation, power verification, reset verification, contention checking is a plus.
Prior experience with silicon debug at the tester and board level, is a plus.
Disclaimer: This job posting and location has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.