Sr DFT Engineer

NXP Semiconductors · Hyderabad

  • Experience6–10 yrs
  • SalaryNot disclosed
  • Work modeunknown
  • Levelsenior
  • Posted19 Sept 2026
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About NXP Semiconductors

NXP Semiconductors is hiring in Hyderabad in semiconductors electronics. This role looks for around 6+ years of experience.

The role

Senior DFT engineer role at a semiconductor manufacturer (NXP Semiconductors) designing, implementing, and verifying DFT architectures for complex SoCs. You will define DFT architecture (scan, MBIST, LBIST, boundary scan), integrate scan insertion and test compression with ATPG patterns, implement memory BIST and logic BIST, and perform DFT verification at RTL and gate-level simulations while supporting ATE teams for test program development and silicon bring-up using ATPG tools, UPF/CPF-based low-power DFT, and fault models (stuck-at, transition, path delay). Location is Hyderabad, Telangana, India; work mode is not stated.

Full job description

Senior DFT Engineer: You will be responsible for designing, implementing, and verifying DFT architectures for complex SoCs. You will work closely with RTL, physical design, and verification teams to ensure robust testability and high-quality silicon.

Key Responsibilities

Define and implement DFT architecture for SoCs (scan, MBIST, LBIST, boundary scan).Develop and integrate scan insertion, test compression, and ATPG patterns.Implement memory BIST and logic BIST strategies.Collaborate with RTL and physical design teams for DFT insertion and timing closure.Perform DFT verification at RTL and gate-level simulations.Work with ATE teams for test program development and silicon bring-up.Optimize test coverage, pattern count, and test time.

Required Skills

Strong expertise in DFT methodologies: Scan, MBIST, LBIST, JTAG.Hands-on experience with industry standard ATPG tools.Proficiency in UPF/CPF-based low-power DFT.Knowledge of fault models (stuck-at, transition, path delay).Familiarity with physical design constraints for DFT.Experience in silicon debug and ATE bring-up.

Preferred Qualifications

Pas experience with SoC level DFTExposure to high-speed interfaces and DFT for mixed-signal blocks.Strong problem-solving and communication skills.

Education

Bachelor’s or Master’s in Electrical/Electronics Engineering.

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