SOC Design Implementation Engineer

Qualcomm · Hyderabad

  • Experience2–7 yrs
  • SalaryNot disclosed
  • Work modeonsite
  • Posted23 Sept 2026
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About Qualcomm

Qualcomm is hiring in Hyderabad in semiconductors electronics. This role looks for around 2+ years of experience.

Skills

  • RTL synthesis
  • Design-for-test
  • MBIST
  • SCAN
  • Timing constraints
  • Static timing analysis
  • Low-power checks
  • Logic equivalence checking
  • Timing closure
  • Constraints debugging

The role

A design engineer at a semiconductor company performs RTL synthesis, design-for-test, and static timing analysis for digital integrated-circuit designs, using low-power checks and timing-closure methods. The role applies logic equivalence checking and constraints debugging to validate gate-level implementations.

Full job description

Job Summary

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Minimum Qualifications

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Responsibilities

RTL Synthesis to achieve the best Performance/Power/Area of the designs

DFT insertions that include MBIST and SCAN, setup Timing Constraints for functional and Test Modes, and Validation.

Run static Low-Power checks on gate level netlists

Verify Logic Equivalency Checks between RTL to Gates and Gates to Gates

Setup signoff Static Timing Analysis and ECO flows and achieve timing closure working with the Design/DFT/PD teams

Timing analysis with STA tools

Constraints debug and sanity checks