Senior Manager ATE SoC validation

Renesas Electronics · Hyderabad

  • Experience12–13 yrs
  • SalaryNot disclosed
  • Work modeonsite
  • Posted28 Sept 2026

About Renesas Electronics

Renesas Electronics is hiring in Hyderabad in semiconductors electronics. This role looks for around 12+ years of experience.

Skills

  • ATE-based SoC validation
  • wafer probe testing
  • final test operations
  • test automation
  • test program development
  • ATE platforms
  • test data analysis
  • yield analysis
  • defect correlation
  • multisite testing
  • parallel testing
  • test time optimization
  • Electrical Engineering

The role

A semiconductor test engineering manager at a semiconductor products company leads ATE-based SoC validation across wafer probe and final test operations, applying test automation and AI/machine learning to test data analytics and defect analysis. The role also directs ATE program development and test strategy.

Full job description

SENIOR MANAGER, ATE SoC VALIDATION

About the Role

We are seeking an experienced Senior Manager to lead ATE (Automated Test Equipment) SoC Validation across wafer probe and final test operations with Hands-on experience with Advantest 93K, Advantest T2000, or Teradyne ATE platforms. You'll drive innovation in test automation and AI-driven analytics, lead high-performing engineering teams, and define next-generation test strategies for advanced semiconductor products.

Key Responsibilities

• Lead and mentor test engineers, test developers, and technicians across wafer probe and final test environments• Drive test automation initiatives and AI/ML-based defect analysis to optimize yield and reduce test cost• Develop and optimize SoC validation strategies, test programs, and coverage metrics using advanced diagnostics• Partner with design, manufacturing, and equipment teams to resolve test-related challenges• Ensure world-class product quality while maintaining DFT compliance and quality standards• Oversee ATE program development, debugging, and optimization across probe and package domains

Required Qualifications

• 12+ years semiconductor test engineering experience (minimum 7 years in ATE-based SoC validation)• Proven expertise managing wafer probe and final test operations• Strong background in test automation, test program development, and ATE platforms• 4+ years of team leadership and people management experience• Bachelor's degree in Electrical Engineering or related field (or equivalent experience)• Experience with test data analysis, yield analysis, and defect correlation• Knowledge of multisite/parallel testing and test time optimization

Good-to-Have Qualifications

• Hands-on experience with Advantest 93K, Advantest T2000, or Teradyne ATE platforms ⭐• Expertise in AI/machine learning applications for test data analytics ⭐• Background in test automation frameworks and automated defect classification• Proficiency in programming languages (C, C++, Python) for test automation• Knowledge of design for testability (DFT) and test compression techniques• Master's degree in related field

What We Offer

• Competitive compensation and comprehensive benefits• Opportunity to work with cutting-edge AI/automation technologies• Leadership of innovative test engineering initiatives• Professional development and growth potential

How to Apply

Submit your resume to me. Highlight your ATE platform expertise, test automation achievements, and AI/ML experience in test analytics.