Physical Design Lead with STA
Advanced Micro Devices (AMD) · Hyderabad
- Experience8–13 yrs
- SalaryNot disclosed
- Work modeonsite
- Levelexecutive
- Posted16 Sept 2026
About Advanced Micro Devices (AMD)
Advanced Micro Devices (AMD) is hiring in Hyderabad in semiconductors electronics. This role looks for around 8+ years of experience.
Skills
- physical design
- place and route
- static timing analysis
- electromigration and IR drop analysis
- physical verification
- SDC
- Tcl
- Perl
- Python
- Makefile
- clock tree synthesis
- synthesis
- low-power design
- machine learning
- Synopsys
- Cadence
- Mentor
The role
A physical design engineer at a semiconductor product company drives RTL-to-GDS execution and SoC physical design closure across CPU, HBM, DDR, and SerDes interfaces, applying static timing analysis and physical verification. The role also develops Tcl, Perl, Python, and Makefile automation for signoff flows and uses machine learning in physical design.
Full job description
Job Summary
The Role: As a member of the PD PnR team responsible for owning and leading SubSystem of 10 partitions. SoC SS PD closure which includes high frequency CPU, HBM, DDR, Serdes interfaces. Will be responsible for RTL to GDS execution with different team members and will work closely with the methodology and CAD teams across various geographies to achieve first pass silicon success.
The Person
A successful person in this role would be able to work in a collaborative team environment working with other business units, central methodology team driving the group signoff and solving the critical issues with vendor.
Strong self-driving ability, should have excellent communication skills (both written and oral)
Key Responsibilities
Owns SS Partitions PnR execution and closure
Drive new improvement in closure
Analysis of data and feedback to Design team
Work with PnR team members for closure convergence starting from Synthesis to Route
Closure signoff on STA, EMIR, PV
Work and collaborate with different business units, CAD and central methodology team to drive the requirement
Automation to refine and improve design signoff requirement and dashboarding
Ability to organize and present complex technical information in a crisp and concise manner.
Interact with other PPA (equivalent) teams internal to AMD
Identify best practices across AMD and industry to update and improve flow/project settings
To increase the competitiveness of each stage in AMD design flow
Ability to work with multi-level functional teams across various geographies.
Highly organized, strong affinity for automation and prioritization.
Preferred Experience
8+ year or more experience design signoff closure
Strong PnR backround with critical problem solving ability on improving PPA and debug
Technical depth in CTS, Route, STA.
EMIR driven power grid knowledge
PnR and STA signoff correlation drive and convergence
Strong at SDC coding and debug skills
Drive new requirements and methodology to aid timing closure at SoC
Identify the gaps and support flows
Strong in scripting, Scripting language experience: TCL, Perl, Python, Makefile.
Drive team towards common requirements and flows
Experienced in deploying and implementing ML techniques and algorithms in physical design.
Low power physical design implementation flows ranging from RTL design through synthesis, place and route, timing closure and physical verification
Experience with different tools from various vendors - Synopsys, Cadence and Mentor.
AMD block TileBuilder and experience in lower tech nodes (5/3/2) is a plus.
Academic Credentials
Bachelors or Masters degree in Computer Engineering / Electrical Engineering
Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.