NPU/AI Processor Synthesis Staff/ Sr Staff/ Technical Lead

Company:

Qualcomm India Private Limited

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

General Summary:

Role Overview

The NPU Synthesis Lead will be responsible for driving synthesis and timing closure for Neural Processing Unit (NPU) IP and subsystems in cutting-edge SoCs. This role involves leading synthesis flows, optimizing for PPA (Performance, Power, Area), and collaborating with architecture, RTL, and physical design teams to ensure high-quality netlists for advanced technology nodes.

Key Responsibilities

Synthesis Ownership

Lead RTL-to-gate-level synthesis for NPU IP and subsystems using industry-standard tools (Synopsys Design Compiler, Cadence Genus).

Develop and maintain synthesis scripts and flows for hierarchical and flat designs.

Timing Closure

Drive pre-layout and post-layout timing closure across multiple voltage and process corners.

Collaborate with STA teams to resolve setup/hold violations.

Power & Area Optimization

Apply physical-aware synthesis techniques to meet aggressive PPA targets.

Implement low-power strategies using UPF/CPF flows.

Constraint Management

Validate and maintain SDC constraints for clocks, I/O delays, multi-cycle paths, and false paths.

Cross-Functional Collaboration

Work closely with RTL design, DFT, and physical design teams for seamless handoff.

Provide feedback to architecture and RTL teams for QoR improvements.

Quality Checks

Perform LEC (Logical Equivalence Check), CLP (Clock/Power checks), and linting.

Flow Innovation

Explore advanced synthesis methodologies and EDA tool capabilities for better QoR.

Team Leadership

Mentor junior engineers and drive best practices across synthesis and timing teams.

Minimum Qualifications:

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

OR

Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.

OR

PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Required Skills

Technical Expertise

Strong knowledge of ASIC design flow: RTL Synthesis STA P&R.

Proficiency in synthesis tools (Design Compiler, Genus) and STA tools (PrimeTime).

Low-Power Design

Experience with UPF/CPF-based flows and multi-voltage designs.

Scripting

Advanced skills in Tcl, Perl, Python for automation.

EDA Tools

Familiarity with Spyglass, Lint, CDC tools, and power analysis tools.

Leadership

Ability to lead synthesis teams and coordinate with cross-functional groups.

Education

Bachelor’s/Master’s in Electrical Engineering, Computer Engineering, or related field.

Experience

15+ years in ASIC synthesis and timing closure, with at least 3 years in NPU or AI processor design.

Preferred

Experience with advanced nodes (5nm/3nm), hierarchical synthesis, and physical-aware flows.

Prior tape-out experience for NPU or DSP cores.

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