Lead RTL Engineer ( Mixed-Signal IPs)
Silicon Labs · Hyderabad
- Experience5–10 yrs
- SalaryNot disclosed
- Work modeonsite
- Posted23 Sept 2026
About Silicon Labs
Silicon Labs is hiring in Hyderabad in semiconductors electronics. This role looks for around 5+ years of experience.
Skills
- Verilog
- SystemVerilog
- mixed-signal IP design
- digital RTL design
- synthesis
- static verification
- lint
- clock-domain crossing
- digital communication protocols
The role
A design engineer at a semiconductor electronics company develops mixed-signal IP using Verilog and SystemVerilog, applies static verification, and implements digital communication protocols.
Full job description
5-10 years of experience in digital RTL design with strong exposure to mixed-signal IP or subsystem development. . Proficiency in Verilog / SystemVerilog and experience with synthesis and static verification flows (lint,CDC).
is a plus. . Good understanding of digital communication protocols (SPI,I2C,APB,AXI).