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Lead DFT Engineer at AMD — Hyderabad

Experience7–8 yrs
SalaryNot disclosed
Work modeonsite
Posted30 Sept 2026

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About AMD

AMD is hiring in Hyderabad in semiconductors electronics. This role looks for around 7+ years of experience.

Skills

ATPG
scan-stitching
post-silicon debug
DFT
SSN
OCC
TAP verification
ICL simulations
pattern retargeting
timing simulations
no-timing simulations
scan pattern generation
Tessent ATPG
multi-die DFT

The role

A design verification engineer at a semiconductor company develops scan patterns and verifies digital designs through ATPG, scan-stitching, and post-silicon debug. The role also applies Tessent ATPG and multi-die DFT practices to support production-ready processor technologies.

Full job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.

LEAD DFT ENGINEER

The Role

We are looking for an adaptive, self-motivative DFT engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The DFT team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.

The Person

You have a passion for modern, digital design, and DFT in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

Preferred Experience

Hands on experience on SSN , OCC , TAP verification (1838 , 1149.1, 1687) ,ICL simulations, Pattern retargeting , timing and no-timing simulations, Post silicon debug . Working experience in multi die DFT is preferable Responsible for scan patterns generation, verification, delivery to Post silicon team and also support for post silicon debug Experience in scan-stitching; and has good knowledge of scan-stitching related conceptsExcellent hands-on ATPG; and is well conversed with the files required to run ATPGKnowledge/experience with Tessent ATPG (mentor) is a plusExperience with post-silicon bring up is a plus

Academic Credentials

Bachelors degree w/7+ years or Masters degree w/5+ years in Electronics engineering/Electrical Engineering

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.