Full Chip Timing Lead

AMD · Hyderabad

  • Experience8–9 yrs
  • SalaryNot disclosed
  • Work modeonsite
  • Levelexecutive
  • Posted15 Sept 2026
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About AMD

AMD is hiring in Hyderabad in semiconductors electronics. This role looks for around 8+ years of experience.

Skills

  • static timing analysis
  • timing closure
  • SoC design
  • SDC coding
  • Tcl
  • Perl
  • Python
  • Makefile
  • place and route
  • physical verification
  • low-power physical design
  • timing ECO
  • multi-voltage closure
  • Synopsys
  • Cadence
  • Mentor

The role

A design engineer at a semiconductor company performs static timing analysis, timing closure, and physical design automation for complex SoC interfaces and signoff flows. The work applies SDC coding, scripting, and low-power physical design across CPU, memory, and high-speed interconnect blocks.

Full job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.

FCT - MTS SILICON DESIGN ENGINEER

The Role

As a member of the PD Full Chip STA closure and optimization team, you will work on SoC Full Chip Timing closure which includes high frequency CPU, HBM, DDR, Serdes interfaces. Will be responsible for SDC validation and timing signoff execution with different team members and will work closely with the methodology and CAD teams across various geographies to achieve first pass silicon success.

The Person

A successful person in this role would be able to work in a collaborative team environment working with other business units, central methodology team driving the group signoff and solving the critical issues with vendor.Strong self-driving ability, should have excellent communication skills (both written and oral)

Key Responsibilities

Owns Full chip Timing Closure Clock build guidance using multiple methods MSCTS, Mesh Design repeater feedback based on timing across blocks Drive new improvement in closure Analysis of data and feedback to PD execution team SDC analysis and feedback Work with PnR engineer for timing convergence Drive the common STA methodology in the business unitWork and collaborate with different business units, CAD and central methodology team to drive the requirementAutomation to refine and improve design signoff requirement and dashboardingAbility to organize and present complex technical information in a crisp and concise manner.Interact with other PPA (equivalent) teams internal to AMDIdentify best practices across AMD and industry to update and improve flow/project settingsTo increase the competitiveness of each stage in AMD design flowAbility to work with multi-level functional teams across various geographies.Highly organized, strong affinity for automation and prioritization.

Preferred Experience

8+ year or more experience design signoff closureTiming closure experience at SoC and block levelTechnical depth in STA, High freq interface closure in hierarchical STA.Multi voltage closureTiming ECO flowHyperscale, Yield analysisPnR and STA signoff correlation drive and convergenceStrong at SDC coding and debug skillsDrive new requirements and methodology to aid timing closure at SoCIdentify the gaps and support flowsStrong in scripting, Scripting language experience: TCL, Perl, Python, Makefile.Drive team towards common requirements and flowsExperienced in deploying and implementing ML techniques and algorithms in physical design.Low power physical design implementation flows ranging from RTL design through synthesis, place and route, timing closure and physical verificationExperience with different tools from various vendors - Synopsys, Cadence and Mentor.AMD block TileBuilder and experience in lower tech nodes (5/3/2) is a plus.

Academic Credentials

Bachelors or Masters degree in computer engineering/Electrical Engineering

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.