Full Chip Timing Lead

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The Role

FCT - MTS Silicon Design Engineer

As a member of the PD Full Chip STA closure and optimization team, you will work on SoC Full Chip Timing closure which includes high frequency CPU, HBM, DDR, Serdes interfaces. Will be responsible for SDC validation and timing signoff execution with different team members and will work closely with the methodology and CAD teams across various geographies to achieve first pass silicon success.

The Person

A successful person in this role would be able to work in a collaborative team environment working with other business units, central methodology team driving the group signoff and solving the critical issues with vendor.

Strong self-driving ability, should have excellent communication skills (both written and oral)

Key Responsibilities

Owns full chip timing closure

Clock build guidance using multiple methods MSCTS, Mesh

Design repeater feedback based on timing across blocks

Drive new improvement in closure

Analysis of data and feedback to PD execution team

SDC analysis and feedback

Work with PnR engineer for timing convergence

Drive the common STA methodology in the business unit

Work and collaborate with different business units, CAD and central methodology team to drive the requirement

Automation to refine and improve design signoff requirement and dashboarding

Ability to organize and present complex technical information in a crisp and concise manner.

Interact with other PPA (equivalent) teams internal to AMD

Identify best practices across AMD and industry to update and improve flow/project settings

To increase the competitiveness of each stage in AMD design flow

Ability to work with multi-level functional teams across various geographies.

Highly organized, strong affinity for automation and prioritization.

Preferred Experience

8+ years or more experience in design signoff closure

Timing closure experience at SoC and block level

Technical depth in STA; high-frequency interface closure in hierarchical STA.

Multi-voltage closure

Timing ECO flow

Hyperscale, yield analysis

PnR and STA signoff correlation drive and convergence

Strong SDC coding and debugging skills

Drive new requirements and methodology to aid timing closure at SoC

Identify the gaps and support flows

Strong in scripting; scripting language experience: TCL, Perl, Python, Makefile.

Drive team towards common requirements and flows

Experienced in deploying and implementing ML techniques and algorithms in physical design.

Low power physical design implementation flows ranging from RTL design through synthesis, place and route, timing closure and physical verification

Experience with different tools from various vendors - Synopsys, Cadence and Mentor.

TileBuilder experience and lower tech nodes (5/3/2) is a plus.

Academic Credentials

Bachelor's or Master's degree in Computer Engineering/Electrical Engineering

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