Full chip Physical verification Engineer
Advanced Micro Devices (AMD) · Hyderabad
- Experience9–14 yrs
- SalaryNot disclosed
- Work modeonsite
- Levelexecutive
- Posted21 Sept 2026
About Advanced Micro Devices (AMD)
Advanced Micro Devices (AMD) is hiring in Hyderabad in semiconductors electronics. This role looks for around 9+ years of experience.
Skills
- Physical verification
- FPGA
- SoC
- RDL development
- Bump development
- Perl
- Tcl
- Python
- SKILL
- LVS/DRC
- PDK
- DRC debugging
- LVS debugging
- Parasitic extraction
- Hierarchical layout
The role
A physical verification engineer at a semiconductor design company integrates FPGA and SoC designs, develops RDL and bump structures, and debugs LVS/DRC checks for advanced-node tapeouts using Perl, Tcl, and SKILL scripting. The role also automates integration flows and handles PDK rule updates.
Full job description
Job Summary
The focus of this role is to lead full chip integration and phsyical verification activities. To actively work on automation of the integration activities thus reducing the human error. Improve the overall efficiency of the team by innovating and executing with leading EDA features.
The Person
Master s/Bachelor s Degree in Electrical/Electronic engineering with 9+ years of experience in FPGA/SOC full chip physical verification, PDK updates, RDL/Bump/Ubump development is required. Strong scripting skills in PERL/TCL/Phython is must.
Successful candidate would be responsible for full chip integration and physical verification of 7nm and lower nodes. You will be actively working with CAD and EDA vendors to improve and automate the integration flows thus by improving the overall fucntional efficiency. This job requires excellent teamwork, great communication and strong problem-solving skill.
Key Responsibilities
SOC RDL development for monolethic and Advanced package technologies.
Full chip integration and physical verification of FPGA/SOC designs
Work closely with PD, CAD, SiTech, EMIR, PKG and EDA vendors for seamless integration of IPs into full chip for ontime tapeout.
Actively work on automation of integration flows to improve the functional efficiency.
Debug the full chip LVS/DRC/Antenna issues with multi point approach and ability to modify the rule files for quicker debug
Preferred Experience
Experience in bump ubump RDL development and 3D integration of AoA or SSIT designs will be desirable.
Should be well versed with FinFet technology DRC debugging and fixes.
Strong debug capabilities with parasitic extraction, LVS/DRC and other Physical verification checks.
Knowledge of scripting languages like SKILL, PERL, TCL etc. is must.
Strong problem solving skills and excellent communication skills.
Sound knowledge of hierarchical layout handling including macros and full chip.
Knowledge in PDK (DRC/LVS rule is preferred.
Academic Credentials
Bachelors or Masters degree in computer engineering/Electrical Engineering
Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.