Dft Engineer - Multiple Levels
Qualcomm · Hyderabad
- Experience4–9 yrs
- SalaryNot disclosed
- Work modeonsite
- Posted23 Sept 2026
About Qualcomm
Qualcomm is hiring in Hyderabad in semiconductors electronics. This role looks for around 4+ years of experience.
Skills
- ASIC design-for-test
The role
A design engineer at a semiconductor company develops ASIC design-for-test solutions using Genus, Synopsys TetraMax, DFTMax, and Cadence Encounter Test, while supporting multiple high-priority chip designs.
Full job description
Working experience in Genus,Synopsys TetraMax / DFTMax and Cadence Encounter Test is a plus. Ability to work in an international team,dynamic environment. Ability to learn and adapt to new tools and methodologies. . Ability to do multi-tasking work on several high priority designs in parallel.
Minimum of 3+ years experience in the area of ASIC / DFT.