Senior Principal Digital Design Engineer — PCIe/CXL

Kandou AI · Greater Hyderabad Area

  • Experience18–19 yrs
  • SalaryNot disclosed
  • Work modehybrid
  • Levelexecutive
  • Posted13 Sept 2026
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About Kandou AI

Kandou AI is hiring in Greater Hyderabad Area in semiconductors electronics. This role looks for around 18+ years of experience.

Skills

  • PCIe
  • CXL
  • SystemVerilog
  • Verilog
  • RTL design
  • Microarchitecture
  • ARM-based SoC
  • AMBA
  • AXI-4
  • CHI
  • ACE
  • Clock Domain Crossing
  • Reset Domain Crossing
  • Low-power design
  • EDA tools
  • Tcl
  • Perl
  • Python
  • Git
  • SVN

The role

A digital design engineer at a semiconductor company defines PCIe/CXL subsystem architecture, develops SystemVerilog RTL, and integrates ARM-based SoC designs with AMBA protocols. The role also applies EDA tools and Python to debug and sign off high-performance interconnect hardware.

Full job description

Location: Greater Bengaluru Area (Hybrid)/ Greater Hyderabad

https://www.thecube.net/events/nyse/ai-factory-data-center-of-the-future/content/Videos/d1ad8af3-1424-4336-a9b3-1d02b5a354b4

we are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable adoption.

Our proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient. Unlike traditional interconnects, our solution reduces power consumption significantly while preserving high bandwidth and ultra-low latency — unlocking unprecedented efficiency for AI training and inference at scale.

our architecture is not just an incremental improvement — it’s a foundational shift in how AI hardware is built for the future.. Location: Hyderabad/Bangalore

Senior Principal Digital Design Engineer — PCIe/CXL

__________________________________________________________________________________________About Kandou AIKandou AI is powering the future of AI infrastructure, operating at the intersection of information theory and semiconductor design. Kandou pioneered Copper MIMO (Chord Signaling) technology, transforming crosstalk and noise inherent in copper links into a mechanism that unlocks higher bandwidth, lower power, and greater scale for GPU, memory, network, and rack-scale connectivity. The company's product portfolio includes the Matterhorn USB4 Retimer, Regli PCIe Retimer, Zetti PCIe Switch, and Glasswing Chiplet Interconnect IP, and it is building next-generation AI systems spanning AI inference, CXL memory platforms, and ultra-high-speed scale-up/scale-out networking.Headquartered in Lausanne, Switzerland, Kandou AI has a global engineering footprint including design centers in the United States, United Kingdom, Germany, Taiwan, and a newly established India Chip Design Headquarters in Hyderabad, reflecting continued investment in world-class semiconductor design talent. Kandou fosters a hybrid, flexible working culture built around autonomy, teamwork, and a shared commitment to pushing the boundaries of connectivity technology.Responsibility and AuthorityNo.Description

1Own and drive PCIe/CXL subsystem micro-architecture definition, RTL implementation, and integration.2Collaborate closely with Architecture teams to translate requirements into robust RTL designs.3Work with Design Verification teams on test-plan reviews, debug, and coverage closure.4Partner with Physical Design and DFT teams to ensure PD-friendly and DFT-ready RTL.5Support silicon bring-up and post-silicon debug, working with firmware and validation teams.6Drive design quality improvements, coding best practices, and reuse across projects.7Participate in design reviews, milestone reviews, and cross-functional technical discussions.8Mentor junior designers and provide technical leadership within the PCIe/CXL design domain.9Individual responsibilities for this role are defined by Kandou's executive team on a project-by-project basis and may vary from this job description.

Required Competencies — EducationNo.Description

1Master's or Bachelor's degree in Electronics/Electrical Engineering (or equivalent), with 18+ years of relevant experience in RTL design.

Required Competencies — ExperienceNo.Description

1End-to-end PCIe/CXL subsystem RTL design execution and sign-off.2Proven experience delivering complex PCIe/CXL IP or subsystems from architecture through RTL closure.3Strong hands-on experience in SystemVerilog / Verilog RTL development.4Expertise in PCIe protocol architecture, including link, transaction, and PHY interaction layers.5Strong understanding of CXL.io, CXL.cache, and CXL.mem architectures.6Deep knowledge of ARM-based SoC integration and AMBA protocols (AXI-4, CHI, ACE).7Experience designing high-performance, low-latency data paths and handling ordering, coherency, and error mechanisms.8Solid grasp of clocking, resets, CDC/RDC, low-power techniques, and performance optimization.9Experience supporting lint, CDC/RDC, synthesis, and design sign-off flows.

Required Competencies — SkillsNo.Description

1Proficient in debugging functional and performance issues at subsystem and SoC levels.2Experience using industry-standard EDA tools from Synopsys, Cadence, and Mentor/Siemens.3Proficient in scripting languages such as Tcl, Perl, or Python.4Experience with version control systems such as Git, SVN, etc.5Strong communication and presentation skills, comfortable interfacing across cross-functional and geographically distributed engineering teams.

SkilsCXLPCIeARM SoCSystemVerilogVerilogMicroarchitecture

ContactUdaymuday_bhaskar@yahoo.comMulya Technologies"Mining the Knowledge Community"