Sr. DFT Engineer
NXP Semiconductors · Delhi
- Experience3–6 yrs
- SalaryNot disclosed
- Work modeunknown
- Levelmid
- Posted11 Sept 2026
About NXP Semiconductors
NXP Semiconductors is hiring in Delhi in semiconductors electronics. This role looks for around 3+ years of experience.
The role
Mid-level Sr. DFT Engineer role at NXP Semiconductors (semiconductor manufacturing) working on Design For Test (DFT) for complex digital designs by defining and implementing DFT architecture (scan, MBIST, boundary scan), performing scan insertion (chain stitching and compression), generating and analyzing ATPG patterns, and debugging DFT issues across design and silicon stages using scan insertion, chain stitching, compression techniques, and ATPG. Work location: Delhi, Uttar Pradesh, India; work mode not specified.
Full job description
Design For Test (DFT) Engineer (Experienced)
We are looking for an experienced DFT Engineer with strong expertise in scan, ATPG, and test methodologies for complex digital designs. The candidate will be responsible for implementing and validating DFT architectures to ensure high test coverage and quality silicon.
Key Responsibilities
Define and implement DFT architecture including scan, MBIST, and boundary scan.Perform scan insertion, chain stitching, and compression techniques.Generate and analyze ATPG patterns to achieve high fault coverage.Debug and resolve DFT-related issues across design and silicon stages.Work closely with RTL, Physical Design, and STA teams for smooth integration.Support pattern validation, gate-level simulations, and silicon bring-up.Ensure compliance with DFT and testability requirements.
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