Senior Lead Verification Engineer

Qualcomm · Delhi

  • Experience5–8 yrs
  • SalaryNot disclosed
  • Work modeonsite
  • Posted23 Sept 2026
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About Qualcomm

Qualcomm is hiring in Delhi in semiconductors electronics. This role looks for around 5+ years of experience.

Skills

  • SoC Design Verification
  • SystemVerilog
  • UVM
  • Verilog
  • SVA
  • PSS
  • SoC architectures
  • RISC-V
  • ARM
  • AXI
  • AHB
  • CHI
  • LPDDR4/5
  • PCIe
  • USB
  • QUP
  • eMMC
  • SD
  • UFS
  • power-aware verification methodologies
  • Python
  • Perl
  • TCL
  • Bash
  • Verdi
  • Gate-Level Simulation

The role

A design verification engineer at a semiconductor technology company develops SoC Design Verification environments using SystemVerilog and UVM for complex processors and subsystems, and applies assertion development and verification methodologies with Verilog and Python automation.

Full job description

Job Summary

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Job Area: Engineering Group, Hardware Engineering

Minimum Qualifications

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.

OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

We are seeking candidates with strong experience in SoC Design Verification and a proven track record in verifying complex SoCs and subsystems.

Key Responsibilities

Solid industry experience in SoC Design Verification.

Strong expertise in developing verification environments and testbenches from scratch at the SoC, subsystem, and IP/core levels.

Hands-on experience with assertion development, debugging, and verification methodologies.

Proficiency in Verilog, System-Verilog, UVM, SVA, and industry-standard verification flows.

Good understanding of SoC architectures, boot flows, CPU architectures (RISC-V/ARM), power management concepts, and system-level verification challenges.

Experience with industry-standard protocols and interfaces such as AXI, AHB, CHI, lpddr4/5, PCIe, USB, qupss, and other peripherals.

Preferred Skills

Preferred Skills: Strong expertise in SoC Design Verification, including System-Verilog/UVM-based verification, testbench architecture, DDR, multimedia subsystems, bus protocols, CPU validation, peripherals, boot flow verification, and power-aware simulation methodologies.

Opportunity

Be part of the verification team responsible for delivering Qualcomm's next-generation mobile and compute SoCs, working on cutting-edge technologies and complex system-level verification challenges.

Job Requirements

5 to 8 years of hands-on experience in SoC Design Verification.

Proven experience in SoC-level testbench architecture, test development, and test plan creation.

Strong understanding of SoC design and verification methodologies.

Hands-on proficiency in Verilog, System-Verilog, UVM, SVA, and PSS.

Experience with industry-standard communication and interface protocols such as PCIe Gen5/6, USB 3.x/4, LPDDR4/5, QUP, eMMC, SD, and UFS.

Knowledge of processor architectures including RISC-V, ARM, and NoC/Interconnect architectures.

Strong understanding of power management concepts and power-aware verification methodologies.

Exposure to Gate-Level Simulation (GLS) is highly desirable.

Proficiency in scripting languages such as Python, Perl, TCL, or Bash for automation and productivity improvement.

Hands-on experience with waveform debugging tools such as Verdi and strong root-cause analysis skills.

Excellent communication, collaboration, and stakeholder management skills, with the ability to work effectively across cross-functional teams.