Senior Lead Physical Design Engineer
Qualcomm · Delhi
- Experience5–10 yrs
- SalaryNot disclosed
- Work modeonsite
- Posted23 Sept 2026
About Qualcomm
Qualcomm is hiring in Delhi in semiconductors electronics. This role looks for around 5+ years of experience.
Skills
- PNR implementation
- Floorplanning
- Placement
- Clock Tree Synthesis
- Post-route implementation
- Static Timing Analysis
- Power analysis
- Formal Verification
- Low power verification
- Physical Verification
- VLSI design
The role
A physical design engineer at a semiconductor company implements chip PNR using floorplanning, placement, CTS, and post-route workflows, and performs signoff analysis with STA, power analysis, and low power verification. The role applies physical implementation and VLSI design expertise to advanced-node chip development.
Full job description
A physical design engineer at a semiconductor company implements chip PNR using floorplanning, placement, CTS, and post-route workflows, and performs signoff analysis with STA, power analysis, and low power verification. The role applies physical implementation and VLSI design expertise to advanced-node chip development.