Senior Lead Physical Design Engineer

Qualcomm · Delhi

  • Experience5–6 yrs
  • SalaryNot disclosed
  • Work modeonsite
  • Posted29 Sept 2026
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About Qualcomm

Qualcomm is hiring in Delhi in semiconductors electronics. This role looks for around 5+ years of experience.

Skills

  • Physical design
  • Static timing analysis
  • Genus
  • Innovus
  • FC
  • PrimeTime
  • Tempus
  • Voltus
  • RedHawk
  • Floorplanning
  • Timing signoff
  • IR drop analysis
  • Physical verification
  • Engineering change orders
  • Perl
  • Tcl

The role

A physical design engineer at a semiconductor technology company plans and optimizes CPU implementation using physical design, static timing analysis, and electronic design automation tools, while applying Perl and Tcl to drive timing closure and power optimization. The role focuses on floorplanning, timing signoff, engineering change orders, physical verification, and low-power implementation.

Full job description

Company

Qualcomm India Private Limited

Job Area

Engineering Group, Engineering Group > Hardware Engineering

General Summary

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Minimum Qualifications

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.

OR

Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

OR

PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Desired Experience

5+ years of experience in Physical design, STA in CPU Domain.Solid understanding industry standard tools for physical implementation [ Genus, Innovus, FC, PT, Tempus, Voltas and redhawk].Solid grip from floorplan to PRO and timing signoff along with understanding of IR drop and physical verification aspect.Should have experienced about preparing complex ECOs for timing convergence [ across huge set of corners] through Tweaker / Tempus / Physical PT ECOs.Should be aware about the tricks for minimizing power.Experience in deep submicron process technology nodes is strongly preferred.Knowledge of high performance and low power implementation methods is preferred.Willing to push PPA to the best possible extent.Strong fundamentals.Expertise in Perl, TCL language

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