Senior DFT Engineer
Qualcomm · Delhi
- Experience3–4 yrs
- SalaryNot disclosed
- Work modeonsite
- Levelmid
- Posted18 Sept 2026
About Qualcomm
Qualcomm is hiring in Delhi in semiconductors electronics. This role looks for around 3+ years of experience.
Skills
- ASIC design
- Design for Test
- scan insertion
- ATPG
- coverage analysis
- timing constraints
- Perl
- shell scripting
- test-vector simulation
- equivalence checking
- DFT DRC
- RTL lint
- TetraMax
- DFTMax
The role
A design verification engineer at a semiconductor technology company develops and validates ASIC and SoC designs through Design for Test, scan insertion, ATPG, and coverage analysis. The role applies Perl and shell scripting to test-vector simulation, timing constraints, and equivalence checks.
Full job description
Company
Qualcomm India Private Limited
Job Area
Engineering Group, Engineering Group > ASICS Engineering
General Summary
As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.
Minimum Qualifications
Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field.
3+ years experience in the area of ASIC/DFT
In depth knowledge of DFT conceptsIn depth knowledge and hands on experience in scan insertion, ATPG, coverage analysis, Transition delay test coverage analysisExpertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violationsExpertise in scripting languages such as perl, shell, etc.Experience in simulating test vectorsKnowledge of equivalence check, DFT DRC rules both in RTL lint tool (like spyglass) and ATPG tool like (TK, TetraMax)Working experience in Synopsis TetraMax/DFTMax and Cadence Encounter Test is a plusAbility to work in an international team, dynamic environmentAbility to learn and adapt to new tools and methodologies.Ability to do multi-tasking & work on several high priority designs in parallel.Excellent problem solving skillsExcellent communication and team work skills and good English is required
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