Principle DFT Engineer
NXP Semiconductors · Delhi
- Experience7–12 yrs
- SalaryNot disclosed
- Work modeunknown
- Levelexecutive
- Posted24 Sept 2026
About NXP Semiconductors
NXP Semiconductors is hiring in Delhi in semiconductors electronics. This role looks for around 7+ years of experience.
The role
Senior DFT Engineer role at NXP Semiconductors for 7–12 years of experience, focused on implementing and verifying scan architectures, performing scan insertion, generating and analyzing ATPG patterns for stuck-at and transition faults, and executing gate-level simulation (GLS) with and without SDF for DFT validation. Requires hands-on expertise in Scan Insertion, ATPG, GLS, Verilog/SystemVerilog, and debugging DFT/GLS issues using industry-standard tools like Mentor/Siemens Tessent, Synopsys, or Cadence. Location is Delhi, Uttar Pradesh, India; work mode not specified.
Full job description
We are seeking an experienced DFT Engineer (7–12 years) with strong hands-on expertise in Scan Insertion, ATPG, and Gate-Level Simulation (GLS) for complex SoC designs. The candidate will be responsible for implementing and verifying scan architectures, performing scan insertion, generating and analyzing ATPG patterns for stuck-at and transition faults, and executing GLS with and without SDF for DFT validation. The role requires close collaboration with RTL, physical design, and test teams to ensure high fault coverage, clean DFT signoff, and timely tape-out support. Proficiency with industry-standard DFT tools (Mentor/Siemens Tessent, Synopsys, or Cadence), solid Verilog/SystemVerilog skills, and the ability to debug DFT and GLS issues independently are essential. Prior experience supporting pre- and post-silicon activities is a plus.
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