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Principal SOC Verification Engineer at NXP Semiconductors — Delhi

Experience10+ yrs
SalaryNot disclosed
Work modeunknown
Levelstaff
Posted19 Sept 2026

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About NXP Semiconductors

NXP Semiconductors is hiring in Delhi in semiconductors electronics. This role looks for around 10+ years of experience.

The role

A Principal SOC Verification Engineer role at NXP Semiconductors (semiconductor manufacturing) requires 10+ years of hands-on end-to-end verification for ARM-based automotive MCUs, including full-chip integration and verification sign-off ownership. You will verify SystemVerilog/UVM-based environments, AMBA protocols (AXI/AHB/APB), ARM Cortex-R52 and Cortex-M7/M4 cores, ARM NIC/XBAR interconnect (connectivity, coherency, performance, deadlock), boot/reset/clocking and low-power behavior, plus MRAM-based subsystems and ISO 26262 safety/firmware-driven flows. You must also perform low-power verification using UPF across multiple power domains (isolation, retention, power state transitions) and lead complex debug efforts. Location is Delhi, Uttar Pradesh, India; work mode is not stated.

Full job description

The Principal SoC Verification Engineer is expected to have 10+ years of hands‑on experience driving end‑to‑end verification for ARM‑based automotive MCUs, with strong expertise in SystemVerilog/UVM‑based environments, full‑chip integration, and verification sign‑off ownership.

The role requires deep knowledge of standard AMBA protocols (AXI/AHB/APB), verification of ARM Cortex‑R52 and Cortex‑M7/M4 cores, and ARM NIC/XBAR interconnect verification, including connectivity, coherency, performance, and deadlock scenarios.

The candidate must demonstrate strong capability in verifying complex subsystem interactions such as boot, reset, clocking, and low‑power behavior. Proven experience in verifying MRAM‑based subsystems, safety mechanisms, and firmware‑driven flows compliant with ISO 26262 automotive safety requirements is mandatory.

A solid understanding of power intent specification and low‑power verification using UPF, covering multiple power domains, isolation, retention, and power state transitions, is required. Pre‑silicon experience on emulation or validation platforms (such as Palladium, Veloce, or equivalent) will be considered a strong add‑on.

The engineer is also expected to lead complex debug efforts, mentor teams, and collaborate closely with design, safety, and validation stakeholders to proactively identify and mitigate verification risks toward tape‑out readiness.

Work Experience and Qualification- At least 10+ years of experience with B. Tech/ M. Tech in electronics and electrical.

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