Lead DFT Engineer
NXP Semiconductors · Delhi
- SalaryNot disclosed
- Work modeunknown
- Levellead
- Posted13 Sept 2026
About NXP Semiconductors
NXP Semiconductors is hiring in Delhi in semiconductors electronics.
Skills
- Scan insertion
- ATPG
- Gate-level simulation
- Mentor Tessent
- Synopsys DFT Compiler
- Cadence Encounter Test
- Fault modeling
- Coverage analysis
- IEEE 1149.1
- IEEE 1687
The role
A digital design engineer in a semiconductor company who develops scan insertion collateral for synthesis, contributes to partition and SoC-level ATPG, and performs DFT GLS simulation using Mentor Tessent, Synopsys DFT Compiler, and Cadence Encounter Test. This person understands DFT architecture, fault modeling, coverage analysis, IEEE 1149.1 JTAG, and IEEE 1687 IJTAG. Core strengths include scan insertion, ATPG, DFT GLS simulation, Mentor Tessent, Synopsys DFT Compiler, Cadence Encounter Test, fault modeling, and coverage analysis.
Full job description
Digital Design Engineer with hand on experience in Scan insertion, ATPG, GLS. He/She will be responsible for understanding the DFT architecture of the design and providing the scan insertion collaterals to the implementation team, to enable scan insertion flows during synthesis. Should have proficiency in industry-standard DFT tools such as Mentor Tessent, Synopsys DFT Compiler, Cadence Encounter Test. Should be able to contribute to ATPG at partition and SoC level. . Should have experience with DFT GLS simulation tools and methodologies, including fault modeling and coverage analysis. Should be familiar with industry standards such as IEEE 1149.1 (JTAG) and IEEE 1687 (IJTAG). Effective communication and teamwork skills, with the ability to collaborate across functions.
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