Lead DFT Engineer
Nxp · Delhi
- Experience3–4 yrs
- SalaryNot disclosed
- Work modeonsite
- Levelmid
- Posted22 Sept 2026
About Nxp
Nxp is hiring in Delhi in semiconductors electronics. This role looks for around 3+ years of experience.
Skills
- Scan insertion
- ATPG
- Gate-level simulation
- Mentor Tessent
- Synopsys DFT Compiler
- Cadence Encounter Test
- Fault modeling
- Coverage analysis
- IEEE 1149.1 (JTAG)
- IEEE 1687 (IJTAG)
The role
A digital design engineer in a semiconductor company who develops design-for-test architecture and enables scan insertion through synthesis. They create scan insertion collateral, contribute to partition and system-on-chip ATPG, and perform gate-level simulation with fault modeling and coverage analysis. Their defining skills are scan insertion, ATPG, and gate-level simulation, alongside Mentor Tessent, Synopsys DFT Compiler, Cadence Encounter Test, IEEE 1149.1 JTAG, and IEEE 1687 IJTAG.
Full job description
Digital Design Engineer with hand on experience in Scan insertion, ATPG, GLS. He/She will be responsible for understanding the DFT architecture of the design and providing the scan insertion collaterals to the implementation team, to enable scan insertion flows during synthesis. Should have proficiency in industry-standard DFT tools such as Mentor Tessent, Synopsys DFT Compiler, Cadence Encounter Test. Should be able to contribute to ATPG at partition and SoC level. . Should have experience with DFT GLS simulation tools and methodologies, including fault modeling and coverage analysis. Should be familiar with industry standards such as IEEE 1149.1 (JTAG) and IEEE 1687 (IJTAG). Effective communication and teamwork skills, with the ability to collaborate across functions.
More information about NXP in India...
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