High Performance DSP core Implementation(Synthesis) Senior Staff Engineer

Qualcomm · Delhi

  • Experience12–13 yrs
  • SalaryNot disclosed
  • Work modeonsite
  • Levelexecutive
  • Posted18 Sept 2026
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About Qualcomm

Qualcomm is hiring in Delhi in semiconductors electronics. This role looks for around 12+ years of experience.

Skills

  • ASIC design
  • Synthesis
  • Physical Synthesis
  • Synthesis methodologies
  • timing constraints
  • Static Timing Analysis
  • timing closure
  • pipelining
  • multi-clock domain design
  • MCMM synthesis
  • Unified Power Format
  • Perl
  • Python
  • Tcl
  • power optimization
  • clock gating
  • netlist delivery
  • ECO
  • formal verification
  • VLSI front-end design
  • Verilog
  • VHDL
  • Quality of Results optimization
  • Equivalence Checking
  • Logic Equivalence Checking
  • low-power design

The role

A VLSI design verification engineer at a semiconductor technology company develops and optimizes ASIC synthesis, physical synthesis, and timing closure for high-performance, low-power designs, using Verilog and Python. Formal verification and power optimization support reliable netlist delivery and multi-clock domain implementation.

Full job description

Company

Qualcomm India Private Limited

Job Area

Engineering Group, Engineering Group > ASICS Engineering

General Summary

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.

Minimum Qualifications

Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.

OR

Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.

OR

PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

Additional Job Description

Experience: 12+ years of hands on experience in Synthesis and LEC

Job Role

Should have strong understanding and in-depth knowledge of Physical Synthesis and Synthesis methodologies with leading industry standard tools.Experience with writing timing constraints for synthesis, STA, timing closure and pipelining at different levels for performance optimization and timing closure.Experience in all aspects of timing closure for multi-clock domain designs.Should be familiar with MCMM synthesis and optimization.Should have good understanding of low-power design implementation using UPF.Experience with scripting language such as Perl/ Python, TCL.Experience with different power optimization flows or technique such as clock gating.Should be able to work independently with design, DFT and PD team for netlist delivery, timing constraints validationShould be able to handle ECOs and formal verification and maintain high quality matrix

Skill Set

Proficiency in Python/TclFamiliar with Synthesis tools (Fusion Compiler/Genus),Fair knowledge in LEC, LP signoff toolsProficient in VLSI front end design steps- Verilog/VHDL, Synthesis, QoR optimization & Equivalence CheckingFamiliarity with standard software engineering practices like VersionControl, Configuration Management, Regression is a plusShould be sincere, dedicated and willing to take up new challenges

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