WiFi MAC Design - Lead Engineer
Qualcomm · Chennai
- Experience3–8 yrs
- SalaryNot disclosed
- Work modeonsite
- Posted23 Sept 2026
About Qualcomm
Qualcomm is hiring in Chennai in semiconductors electronics. This role looks for around 3+ years of experience.
Skills
- Microarchitecture
- Computer Arithmetic
- Circuit Design
- Synthesis
- Formal Verification
- Conformal Low Power
- PTPX
- PrimeTime
- UPF
- RTL
- DFT
- timing constraints
- MCMM
- SAIF
- multibit mapping
- standard-cell libraries
- memory macros
The role
A design engineer at a semiconductor electronics company leads WiFi MAC design using formal verification and power optimization for high-speed, low-power modem hardware. The role applies synthesis and timing analysis to complex digital blocks and guides implementation toward area, timing, power, and testability goals.
Full job description
Company: Qualcomm India Private Limited
Job Area: Engineering Group, Engineering Group > Hardware Engineering
General Summary
Strong fundamentals in core areas: Microarchitecture, Computer Arithmetic, Circuit Design, Process Technology
Strong communication skills to work with design teams worldwide
Extensive experience in Synthesis (DC or Genus), Formal Verification (LEC / Formality), Conformal Low Power, PTPX, Primetime, Conformal ECO
Extensive experience in UPF based power intent and synthesi
Minimum Qualifications
Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
Responsibilities
High-speed and Low-power 5G and WLAN Modem Hardmacro Implementation Lead
Lead, train and mentor team of junior engineers to execute on a complex project for a large modem design in advanced process nodes
Work closely with RTL, DFT and PD leads worldwide to take a project from Post-RTL to Netlist release, and converge on area, timing, power and testability
Primary tasks include writing timing constraints, synthesis, formal verification, CLP, Primetime, PTPX, CECO
Optimize datapath design for low-area, low-power and high-speed using advanced features in synthesis such as MCMM, SAIF, multibit mapping etc.
Optimize PPA using the right tool options and stdcell libraries / memories
Handle complex digital blocks with >1M gates in advanced process nodes from 4nm / 5nm / 7nm / 8nm