Staff Engineer - SoC Power Architecture
Qualcomm · Bengaluru
- Experience8–9 yrs
- SalaryNot disclosed
- Work modeonsite
- Posted22 Sept 2026
About Qualcomm
Qualcomm is hiring in Bengaluru in semiconductors electronics. This role looks for around 8+ years of experience.
Skills
- Dynamic Power Optimization
- Vmin Analysis and Margining
- Leakage Power Reduction
- Low-Power Design Techniques
- PDN/Power Integrity Analysis
- DVFS
- Clock Gating
- Power Gating
- MATLAB Modeling
- SPICE Simulations
- Lab power/perf data crunching
The role
A power architecture engineer at a semiconductor company develops SoC power architectures using low-power design techniques and power integrity analysis, applying MATLAB Modeling, SPICE Simulations, and DVFS to optimize energy, voltage, and thermal behavior. Expertise also covers clock gating and power gating.
Full job description
Company
Qualcomm India Private Limited
Job Area
Engineering Group, Engineering Group > Systems Engineering
General Summary
Seeking an experienced SoC Power Architect to drive power-efficient architectures for next-generation SoCs. The role focuses on optimizing & exploring new features to optimize dynamic power , Vmin reduction, leakage power , use case energy footprint across SOC infra , CLK tree power, power modelling including lab characterization of SOC infra energy impacts & residency profiles of use-cases, data analysis
Key Responsibilities
Exploring new SoC-level power architecture & optimization features, architecture dependencies with different IP blocks. Driving cross-functional technical evaluations of new features across multiple stakeholdersEnergy & latency sensitivity study of dynamic power reduction techniques DVFS, clock gating, power gating, Micro/Macro power collapse periodsAnalyze and optimize Vmin margins, power-performance tradeoffs, and silicon robustness.SOC infrastructure power optimization techniques by studying infra utilization based on use-case profiles ,Island use-cases flows, constraints in micro & macro -idle power optimization techniques, Drive leakage reduction and low-power design techniques across advanced process nodes.Evaluate efficient techniques to manage voltage droops, overshoots, thermal & electrical limits Handson experience in developing MATLAB models to quantify PPA KPI of power architecture features SPICE simulations to backup SOC/System level architecture features heling optimize Voltage droops, overshoots dynamic load-line management
Required Qualifications
Bachelor's/Master's degree in Electrical/Electronics Engineering or related field.8+ years of experience in SoC Power Architecture, Energy Management & Low-Power Design.Strong expertise in:Dynamic Power OptimizationVmin Analysis and MarginingLeakage Power ReductionLow-Power Design TechniquesPDN/Power Integrity AnalysisDVFS, Clock Gating, Power Gating
Hands-on experience with:MATLAB Modeling, SPICE Simulations, Lab power/perf data crunching
Minimum Qualifications
Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience.
OR
Master's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience.
OR
PhD in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience.
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