Staff Engineer -DFT

Company: Arm

Key Skills: DFT, MBIST, Serdes, JTAGRoles and Responsibilities: Perform DFT verification of mixed-signal IP blocks in complex SoCs.Own verification and debug of DFT features across block and SoC levels.Develop, verify, and debug ATE test patterns and drive pattern bring-up on silicon.Perform ATE pattern debug and stabilization, including root-cause analysis of simulation-to-silicon and tester-related failures.Work extensively with JTAG (IEEE 1149.1) and iJTAG (IEEE 1687) architectures and associated verification flows.Develop and maintain PDL (Procedural Description Language) for embedded instruments and iJTAG networks.Generate, validate, and debug DFT patterns using Siemens Tessent tools.Debug complex pattern, timing, protocol, and DFT infrastructure issues across simulation and ATE environments.Collaborate closely with DFT, design, verification, physical design, product engineering, and test engineering teams during pre-silicon and post-silicon phases.Drive technical issues independently from initial investigation through root-cause identification and final resolution.Skills Required:10+ years of hands-on experience in DFT and DFT verification.Strong hands-on experience with verification of mixed-signal blocks from a DFT perspective.In-depth understanding of ATE architecture, test programs, pattern formats, and pattern execution/debug flows.Proven experience in:Loopback test verification for high-speed SERDES blocks such as UCIe, DDR PHY, PCIe/Ethernet, and USB, based on BIST.Sensors and calibration procedures.Lane repair schemes.ATE pattern bring-up and debug.Pattern stabilization.Failure analysis and root-cause debugging.Test-time reduction and optimization.Knowledge of SCAN and MBIST is a plus.In-depth understanding of JTAG and iJTAG protocols, including IEEE 1149.1 and IEEE 1687.Education: Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Microelectronics, or a related field, with relevant industry experience.