Staff Engineer CPU IP Design Engineer

About MIPS @ GlobalFoundries:

GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies.

With the addition of the MIPS team, GF now offer a rich portfolio of RISC-V CPUs, especially AI-enabled processors for the Physical AI world.

Summary Of Role

We are seeking an experienced CPU IP Design Engineer. Responsible for Defining, leading and owning RTL development of our latest AI-enabled RISC-V CPU core. The candidate will be responsible for all aspects of the design including Functional Features, Performance, Power, and Area.

Essential Responsibilities

Drive the micro-architecture and design of critical blocks of the CPU coreDesign of RISC-V Vector CPU core and its custom extensionsDesign of AI-enabled Matrix engine to augment the Vector CPUExplore high-performance strategies working with the CPU modeling teamPerform Microarchitecture development and specification- from early high-level architectural exploration, through microarchitectural research and arrive at detailed specificationsConfigure Design Features Development, assessment, and refinement of RTL design to target power, performance, area, and timing goalsPerform Functional verification support and assist in the design verification strategyAssist with the verification of RTL design performance goalsPartner with a multi-functional engineering team to implement and validate physical design aspects of timing, area, reliability, testability, and power

Other Responsibilities

Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs.

Required Qualifications

Hands-on working knowledge of the pipeline stages of an in-order or out-of-order high-performance CPU coreThorough knowledge of microprocessor architecture including expertise in one or more of the following areas:Instruction fetch and decode, branch prediction techniquesInstruction scheduling, register renaming, Reorder Buffer (ROB)Out-of-order executionInteger and Floating-point executionLoad/Store executionInstruction and Data PrefetchVector data pathCache and memory subsystemsKnowledge of Cache coherency and memory consistencyKnowledge of System Verilog, Verilog and/or VHDLExperience with simulators and waveform debugging tools.Knowledge of logic design principles along with timing and power implicationsMaster’s with 4-7 years of experience, PhD 2-5 years of work experience

Preferred Qualifications

Experience with designing RISC-V, ARM, and/or MIPS CPUExperience with Hardware multi-threading, virtualization, and SIMD designsExperience with vector and matrix-enabled CPUs, preferably RISC-V processors.Understanding of high-performance techniques and trade-offs in a CPU microarchitectureUnderstanding of low-power microarchitecture techniquesExperience using a scripting language such as Perl or PythonUnderstanding of CPU integration at SoC levelUnderstanding of Safety and Security microarchitecture

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