STA methodology engineer
NXP Semiconductors · Bengaluru
- Experience10–12 yrs
- SalaryNot disclosed
- Work modeunknown
- Levelstaff
- Posted12 Sept 2026
About NXP Semiconductors
NXP Semiconductors is hiring in Bengaluru in semiconductors electronics. This role looks for around 10+ years of experience.
The role
Staff STA Methodology Engineer role at a semiconductor manufacturing company (NXP Semiconductors) in Bengaluru, India, with 10–12 years of experience. You benchmark logic libraries across technology nodes (40nm, 14nm, 10nm, 7nm, 5nm) using synthesis and PNR-based flows and perform STA including timing analysis, DRCs, annotation issues, multivoltage flow enablement, noise and crosstalk analysis. Required skills include STA concepts, timing constraints, closure methodologies, DRC handling, annotation, multivoltage flows, noise and crosstalk, plus Python scripting and STA flow automation; familiarity with industry-standard EDA tools and flows is expected. Location is Bengaluru, Karnataka, India; work mode is not specified.
Full job description
Job Title: STA Methodology Engineer
Team: CTO-DE-FDIP-Logic Libraries
Location: Bengaluru
Experience Level: 10–12 Years
Employment Type: Full-Time
Role Overview
We are seeking a highly skilled and experienced STA Methodology Engineer to join our CTO-DE-FDIP-Logic Libraries team. In this role, you will be responsible for benchmarking various logic libraries across multiple technology nodes (40nm, 14nm, 10nm, 7nm, 5nm) using synthesis and PNR-based flows on real-world chips and blocks. You will collaborate closely with Timing Methodology and Signoff teams to ensure robust and efficient STA methodologies.
Key Responsibilities
Benchmark logic libraries across advanced technology nodes using synthesis and PNR flows.Collaborate with cross-functional teams to validate and refine timing constraints.Develop and maintain benchmarking frameworks for constraint validation and STA methodology evaluation.Perform comprehensive STA including timing analysis, DRCs, annotation issues, multivoltage flow enablement, noise and crosstalk analysis using Logic Libraries Integration flow checks.Contribute to the development and automation of STA flows and methodologies.
Required Qualifications
Bachelor’s or Master’s degree in Electrical or Electronics Engineering.10–12 years of hands-on experience in STA, with proven tape-out experience as a block owner or lead.Deep understanding of STA concepts, timing constraints, and closure methodologies at both block and SoC levels.Proficient in handling timing-related issues such as DRCs, annotation, multivoltage flows, noise, and crosstalk.Strong collaboration skills and ability to work across teams to drive methodology improvements.
Preferred Skills
Proficiency in Python scripting.Overview/understanding of AI/GenAI would be added advantage.Experience in developing or enhancing STA flow automation.Familiarity with industry-standard EDA tools and flows.
Soft Skills
Self-motivated with a proactive approach to problem-solving.Strong communication and interpersonal skills.Ability to work independently and as part of a global team.
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