Sr. Staff Engineer PD
GlobalFoundries · Bengaluru
- Experience4–5 yrs
- SalaryNot disclosed
- Work modeonsite
- Levelmid
- Posted15 Sept 2026
About GlobalFoundries
GlobalFoundries is hiring in Bengaluru in semiconductors electronics. This role looks for around 4+ years of experience.
Skills
- Design for Test
- synthesis
- floorplanning
- placement
- clock tree synthesis
- place-and-route
- static timing analysis
- power analysis
- congestion mitigation
- physical verification
- Design Rule Checking
- Layout Versus Schematic
- Tcl
- Python
- Perl
- RTL-to-GDSII
- multi-corner multi-mode analysis
- IP integration
- Electronic Design Automation
The role
A physical design engineer at a semiconductor company develops custom silicon using Design for Test, static timing analysis, and electronic design automation, and automates design flows with Tcl scripting and Python. The work spans synthesis, place-and-route, timing closure, power analysis, physical verification, and tape-out for customer-specific integrated circuits.
Full job description
The Physical Design Engineer delivers hands-on expertise in designing and implementing custom silicon solutions to meet detailed customer requirements. This role executes physical design flows—including synthesis, place-and-route, and verification—while applying standardized methodologies for efficient IP reuse, rapid turnaround, and high-quality tape-outs.
Your Job
Implement DFT architectures including ATPG, MBIST, LBIST, scan insertion, and analog test features Execute all phases of physical design: synthesis, floorplanning, placement, clock tree synthesis, place-and-route, timing closure, power/noise analysis, and signoff verification.Implement design strategies to achieve performance, area, and power targets for customer-specific ICs under lead guidance.Apply re-use methodologies, leveraging standard IP blocks, libraries, and flows to accelerate project execution.Resolve timing, congestion, and power issues in high-speed, high-density designs using EDA tools and scripting.Collaborate with RTL design, verification, DFT, and package teams to integrate requirements and ensure design convergence.Perform physical verification (DRC, LVS) and support debug for clean tape-out deliverables.Automate flows with TCL, Python, or Perl scripts to improve productivity and repeatability.Analyze design metrics and contribute to process improvements through data-driven insights.
Other Responsibilities
Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs.
Required Qualifications
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.4+ years of hands-on physical design experience on SoCs, covering RTL-to-GDSII flows.Proficiency with EDA tools like Synopsys ICC2/Fusion Compiler, Cadence Innovus/Genus, or Mentor Calibre for synthesis, PNR, STA, and verification.Strong knowledge of STA (PrimeTime/Tempus), power analysis, and congestion mitigation techniques.Experience with scripting (TCL, Python, Perl) for flow automation and debugging.Familiarity with advanced nodes, multi-corner multi-mode (MCMM) analysis, and IP integration.Analytical mindset for tackling complex timing/power challenges and effective cross-team communication.
Preferred Qualifications
Experience with custom silicon for automotive, high-performance computing, or AI applications.Proactive in adopting new tools, flows, and best practices for re-use and efficiency.Detail-oriented team player committed to quality and on-time delivery.
Information about our benefits you can find here: https://gf.com/about-us/careers/opportunities-asia