Sr Staff Engineer EM/IR

Job Summary

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Qualifications

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.

Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.

PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

Responsibilities

Sign-off Ownership:

Own full-chip and block-level static/dynamic IR drop and signal/power electromigration sign-off.

Own die plus interposer analysis, die plus interposer plus pkg analysis.

Should have expertise in handling vector based IR signoff and vector less signoff in different modes

Drive root-cause debugging for voltage, EM violations and collaborate with physical design (PD) teams on floorplanning and power grid fixes.

Own power estimation and signoff on Primepower and Joules on different use cases

Should have knowledge of CPM generation on different use cases

Understand Mixed signal IP requirements and derive metrics for signoff

Flow Development:

Define and maintain robust EMIR methodologies using standard EDA tools like Ansys RedHawk-SC, or Cadence Voltus.

Work on enhancing flow and methods for faster convergence and covering critical gaps with changing signoff trends.

Cross functional:

Support chip-package-system (CPS) integration and work alongside silicon package and interposer teams.

Work closely with PnR on fixes needed for EMIR violations and left shift strategy for correct by construction methods

Work with DFT teams to understand impact of DFT strategy on EMIR, assess/fix impact on IR from DFT patterns, provide guidelines for toggling activity in DFT modes, provide power estimation to ATE and board testing teams.

Work proactively with EDA vendors to get resolution on Tool issues, track critical issues impacting project, initiate and track topics of long term and future interests.

Work with flow teams to integrate new methods and fixes in to the flow that are impacting ongoing projects. Initiate work flows for long term and future interests.

Leadership Management Responsibilities

Team Guidance: Direct daily task allocation, monitor metrics, and manage project schedules to meet tapeout milestones.

Mentorship: Train junior and mid-level engineers in advanced-node power integrity challenges and scripting (TCL, Python).

Cross-Functional Collaboration: Partner with timing (STA), physical design, package/interposer and analog/SerDes integration groups to clear design bottlenecks.

Stakeholder Reporting: Communicate technical risks, execution progress, and mitigation paths to upper management on a regular basis.

Skills

RedHawk_SC

Voltus

PTPX

EMIR

Python

TCL

STA

DFT