Sr Lead Engineer - Post Si Validation

Company

Qualcomm India Private Limited

Job Area

Engineering Group, Engineering Group > ASICS Engineering

General Summary

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.

Minimum Qualifications

Bachelor's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.

OR

Master's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

OR

PhD in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.

Responsibilities

You will be part of Qualcomm Snapdragon SoC - Silicon Validation team, particularly in the bring up of SVE convex infra, IST framework for the enablement of VI content in production.Understand the IP architecture, work with IP validation teams and Systems validation Lead/system content engineer to understand the validation requirements, develop/port/enhance the validation software content and bring up.Own SoC frequent regression and execute end-to-end regression suite by considering SoC design corner cases wrt power and performance.Executing SOC validation releases on bench in lab and supporting the SLT teams in Debug and enabling different features in the framework.Use silicon debug hooks to measure power/performance/coverage and other KPI metricsWork with a relevant team member for regular reporting of issues and failure of debugs.

Mandatory Skills

Basics of processor architecture, Multicore/Multiprocessor with SMP/MTE/heterogenous cores. C language expertise for low level programming, Assembly language for any processor, C-assembly interworking Operating systems/RTOS/Linux kernel internals, scheduling policies, locking mechanism, MMU/paging etc Exposure to working on emulation/pre-si environment is added advantage Using JTAG based debuggers, compilers/linkers Should have good exposure to software development life cycle

Desired Skills

Exposure to SoC architecture paradigms – interconnects, power management, Software development for silicon enablement, silicon validation Bring-up of hardware-software solution on FPGA/emulation platforms and on fresh SOC designs Software for power/performance KPIs Good knowledge of ARM Cortex-A7/A8) / x86 / PowerPC CPU and memory system architecture Weakly ordered memory model/pipelining of memory systems/memory barriers Software development towards higher performance of multi-threaded applications using lower power Top level of ASIC design methodology is an added skill

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