Sr Design Engineer

NXP Semiconductors · Bengaluru

  • Experience2–4 yrs
  • SalaryNot disclosed
  • Work modeonsite
  • Posted25 Sept 2026
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About NXP Semiconductors

NXP Semiconductors is hiring in Bengaluru in semiconductors electronics. This role looks for around 2+ years of experience.

Skills

  • Custom IO circuit design
  • Analog circuit design
  • CMOS device physics
  • ESD design methodologies
  • Cadence Virtuoso
  • SPICE
  • LVS
  • DRC
  • EMIR
  • Monte Carlo analysis

The role

A design engineer at a semiconductor company designs custom IO circuits and develops signal integrity analysis using Cadence Virtuoso and SPICE-based simulators. The role applies CMOS device physics, ESD design methodologies, silicon validation, and Python.

Full job description

Key Responsibilities

Design and develop custom IO circuits including:GPIOLVDSLVCMOSSSTLHSTLDDR InterfacesHigh-speed SerDes support circuitsPerform transistor-level design and simulation using advanced CMOS technology nodes.Develop and optimize:ESD protection circuitsLevel shiftersInput buffersOutput driversOn-chip termination circuitsConduct pre-layout and post-layout simulations for functionality, timing, power, noise, and reliability.Perform signal integrity analysis including:IBIS model generationPackage-aware simulationsCrosstalk and reflection analysisDrive layout reviews and work closely with physical design teams to ensure design quality and performance targets.Support silicon bring-up, characterization, debugging, and production ramp activities.Collaborate with system, package, reliability, and product engineering teams.Develop and maintain design documentation, specifications, and verification reports.

Required Qualifications

Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Microelectronics, or related field.2-4 years of experience in Analog/Mixed-Signal or IO Circuit Design.Strong understanding of:CMOS device physicsAnalog circuit design fundamentalsIO architectures and standardsESD design methodologiesHands-on experience in custom circuit design using Cadence Virtuoso.Expertise in SPICE-based simulators such as Spectre, HSPICE, or FineSim.Experience with advanced technology nodes (16nm/7nm/5nm preferred).Good knowledge of LVS, DRC, EMIR, and reliability checks.Familiarity with process corners, Monte Carlo analysis, and yield optimization techniques.

Preferred Skills

Experience with DDR4/DDR5, LPDDR, USB, PCIe, MIPI, or Ethernet interfaces.Knowledge of package modeling and SI/PI analysis tools.Understanding of ESD standards such as HBM, CDM, and IEC.Experience in silicon validation and lab characterization.Scripting skills in Python, Perl, Tcl, or SKILL.Familiarity with IBIS and IBIS-AMI model generation.

Desired Competencies

Strong analytical and debugging skills.Excellent communication and cross-functional collaboration.Ability to lead technical discussions and mentor junior engineers.Proven track record of delivering silicon successfully from specification to production.Self-driven with strong problem-solving abilities.

Nice to Have

Experience in automotive, AI/ML, networking, mobile, or data center SoCs.Exposure to functional safety and reliability requirements.Prior ownership of complete IO IP development cycle.

This role is ideal for an engineer who has hands-on experience in IO circuit design, ESD, signal integrity, and silicon validation, and is looking to contribute to next-generation semiconductor products.

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