SoC Verification Engineer | UVM & System Verilog Specialist

Texas Instruments · Bengaluru

  • Experience3–5 yrs
  • SalaryNot disclosed
  • Work modeonsite
  • Posted26 Sept 2026
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About Texas Instruments

Texas Instruments is hiring in Bengaluru in semiconductors electronics. This role looks for around 3+ years of experience.

Skills

  • UVM
  • SystemVerilog
  • C
  • Python
  • Perl
  • Shell
  • Verilog
  • VHDL
  • bus protocols
  • digital design
  • computer architecture
  • Cadence Xcelium
  • Cadence vManager
  • Formal verification
  • ISO 26262

The role

A design verification engineer at a semiconductor company defines verification strategy, builds UVM and SystemVerilog environments, and validates SoC designs through functional and post-silicon verification. Work includes bus protocols and functional safety verification.

Full job description

Responsibilities:

Complete ownership of IP/subsystem/SOC DV ownership right from spec definition till the post silicon verification and solving the customer issues on need basis. This includes:

Active involvement with architecture team during the spec definition phaseVerification strategy definition along with Verification plan to meet 100% spec to regression traceability along with signoff metricsSubSystem/SOC verification covering functional and Firmware scenarios in RTL/PARTL, GLS/PAGLS modes.DV Environment ownership: TB development/enhancements including checkers and coverage monitor definitions along with DV flow updates as per the project needsActive collaboration with cross functional teams -Architecture, RTL, PD, DFT, Systems, Analog, FW and application teams -to enable the Verification goals for IP/Subsystem/SOC starting from spec definition till post silicon verification closure activitiesFinal SoC DV signoff based on Regressions, coverage metrics, DV to spec traceability using C and/or SV-UVM adhering to ISO26262 guidelines

Qualifications:

• 3- 5 of DV experience in SS/SOC/Post silicon DV with a Bachelor or Master’s degree in EE/ECE/CS or related specializations

Skills:

Experience in one or many of the following: C based SOC DV, scripting (Python/Perl/Shell) knowledge, DV flow ownership for functional/Formal verification, UVM/System Verilog deep understanding, AMS/GLS/PAGLS/CPF/UPF based verification, Post silicon verification etc.Strong in digital design fundamentals, computer organization & architectures and bus protocolsExcellent debugging skills with Verilog/VHDL designsThorough knowledge in one or many of the standard protocols. Ex: AXI, AHB, APB, CAN, Ethernet, I2C, SPI, UART, PSI5, Flexray etcWork experience on C based environment with ARM/DSP multi-processor-based systems including the power aware simulations is a big plusGood problem-solving skillsExperience with Cadence tools (Xcelium/vManager/Formal applications/safety simulator) or similar tools/DV flowsExposure to CDC DV, Post silicon verification and functional safety is an added advantageEffective communication skills to interact seamlessly with all stakeholdersMust be highly focused and remain committed to obtaining closure on project goals