SMMU Senior Lead Design Verification Engineer
Qualcomm · Bengaluru
- Experience3–8 yrs
- SalaryNot disclosed
- Work modeonsite
- Posted23 Sept 2026
About Qualcomm
Qualcomm is hiring in Bengaluru in semiconductors electronics. This role looks for around 3+ years of experience.
Skills
- SystemVerilog
- UVM
- ARM SMMU
- AXI
- AHB
- APB
- CHI
- Virtual Memory
- SoC system architecture
- Functional coverage
- Code coverage
- Hardware debugging
The role
A design verification engineer in a semiconductor product company develops SystemVerilog and UVM testbenches for ARM SMMU-based SoC memory systems, validating coverage and debugging hardware failures. The role also applies AXI, AHB, APB, and CHI protocols to analyze system behavior and resolve post-silicon issues.
Full job description
General Summary:
As a leading technology innovator, Qualcomm pushes the boundaries of what''s possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.
Minimum Qualifications :
Bachelor''s degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORMaster''s degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
General Summary:
Ownership of System Memory Management [SMMU] IP test bench and collaterals for the next generation System-on-chip (SoC) for smartphones, tablets and other product categories. System Memory Management Unit does virtual to physical address translation, dynamic allocation and access control of DDR memory, designed as per ARM SMMU architecture spec.
Job responsibilities include
Ownership of DV test bench and other associated collaterals (Checkers, Trackers, Scoreboards, Assertion, Functional Coverage)
Develop test plan and test cases to cover design feature set, follow up with stake holders on code coverage, functional coverage closure at different levels of test bench
Work closely with System Architects, Design, emulation teams on failure debugs, code/functional coverage closure
Debug of regression signatures and identifying bug fixes
Developing/Deploying scripts/tools for validation (Certitude, VC Formal, Fishtail)
Debug and root cause post silicon issues in collaboration with Design, SW and test teams
Work with SoC level performance modeling team on latency, bandwidth analysis
Required skillset include
Strong debugging, Analytical and problem-solving skills
Expertise on UVM, System Verilog coding
Knowledgeable about ARM bus protocols (AXI, AHB, APB, CHI), Virtual Memory concepts, SoC system architecture
Experience in developing Monitors, Scoreboards, Sequencers that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved
Post-si bring-up and HW-SW debug experience would be a plus. Knowledge exposure to silicon debug tool chains would be an added advantage
Communication and collaboration skills to work with a large world-wide design organization