Silicon Engineer
Google · Bengaluru
- Experience1–2 yrs
- SalaryNot disclosed
- Work modeonsite
- Leveljunior
- Posted14 Sept 2026
About Google
Google is hiring in Bengaluru in technology software. This role looks for around 1+ years of experience.
Skills
- ASIC verification
- SystemVerilog
- UVM
- Design verification
- Coverage-driven verification
- Power-aware simulation
- Formal verification
The role
A design verification engineer at a semiconductor technology company plans ASIC verification, builds SystemVerilog and UVM environments, and validates power-management features through formal verification. Coverage-driven verification and computer architecture expertise support robust digital design quality.
Full job description
Google is hiring for the role of Silicon Engineer!
Responsibilities of the Candidate:
Provide test plans, including verification strategy, environment, components, stimulus, checks, and coverage, and ensure documentation is easy to use.
Plan the verification of digital design blocks by understanding design specifications and collaborating with design engineers to identify key verification scenarios.
Create and improve constrained-random verification environments using SystemVerilog and UVM. Optionally use SystemVerilog Assertions (SVA) and formal tools for formal verification.
Perform power-aware simulations and formal verification to validate power management features like clock gating, power gating, and DVFS. Develop and implement power-aware test cases, including stress and corner-case scenarios, for power integrity.
Develop and execute coverage-driven verification plans to ensure comprehensive coverage of ASIC designs. Collaborate with design engineers to resolve coverage issues and improve design quality.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
1 year of experience with creating/using verification components and environments in UVM methodology at IP or Subsystem level.
Experience developing and maintaining design verification (DV) testbenches, test cases, and test environments.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience with image processing, computer vision or machine learning IPs.
Experience with AMBA (APB/AXI/ACE) or other standard protocols.
Familiarity with CPU, GPU or other computer architectures.