Senior STA Design Engineer

AMD · Bengaluru

  • Experience4–5 yrs
  • SalaryNot disclosed
  • Work modeonsite
  • Posted24 Sept 2026
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About AMD

AMD is hiring in Bengaluru in semiconductors electronics. This role looks for around 4+ years of experience.

Skills

  • static timing analysis
  • SDC constraints
  • Tcl
  • timing closure
  • timing analysis
  • Synopsys Design Compiler
  • Synopsys PrimeTime
  • OCV
  • AOCV
  • POCV
  • Linux

The role

A design verification engineer at a semiconductor company develops static timing analysis for silicon designs, using Synopsys Design Compiler/PrimeTime and Tcl scripting for timing closure. The role applies SDC constraints, OCV analysis, and design-for-test timing requirements across blocks and full-chip implementation.

Full job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.

SENIOR STA SILICON DESIGN ENGINEER

Key Responsibilities

Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoffEnsuring constraints quality (SDC) using industry tools like Fishtail , GCADrive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checksRequires a mix of SDC knowledge, EDA timing tool competence and Tcl based scripting capability (in both EDA environment and standalone Linux Tcl shell scripts)Responsible for Timing closure of one or multiple sub chip/subsystem OR Full chip.Ensuring Subsystem/full chip level Interface timing closure along DRV closureGenerating timing ECO using tools DMSA/Tweaker.

Preferred Experience

4-5 years of experience in building the timing constraints for IPs, blocks and Full-chip implementation in both flat/hierarchical flows.Experience with analyzing the timing reports and identifying both the design and constraints related issues.Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail, Tweaker etc.Experience in timing closure of high frequency blocks & subsystems (> Ghz range )Good Understanding of DFT modes requirements for timing signoffGood understanding of SDC constraints, OCV,AOCV,POCV analysis.Strong TCL/scripting knowledge is mandatory.

ACADEMIC CREDENTIALS:

Bachelors or Masters degree in computer engineering/Electrical Engineering

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.