Senior Engineer - DFT

Qualcomm · Bengaluru

  • Experience4–9 yrs
  • SalaryNot disclosed
  • Work modeonsite
  • Posted23 Sept 2026
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About Qualcomm

Qualcomm is hiring in Bengaluru in semiconductors electronics. This role looks for around 4+ years of experience.

Skills

  • ASIC/DFT
  • DFT concepts
  • scan insertion
  • ATPG
  • coverage analysis
  • transition delay test coverage analysis
  • test mode timing constraints
  • Perl
  • shell scripting
  • test vector simulation
  • equivalence checking
  • DFT DRC
  • RTL lint
  • ATPG tools

The role

A design verification engineer at a semiconductor technology company develops ASIC/DFT solutions using scan insertion and ATPG, analyzes test coverage and timing constraints, and applies Perl scripting. The role also uses equivalence checking and RTL verification tools.

Full job description

Job Summary

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Minimum Qualifications

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.

PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Requirements

Minimum of 3+ years experience in the area of ASIC/DFT

In depth knowledge of DFT concepts

In depth knowledge and hands on experience in scan insertion, ATPG, coverage analysis, Transition delay test coverage analysis

Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations

Expertise in scripting languages such as perl, shell, etc.

Experience in simulating test vectors

Knowledge of equivalence check, DFT DRC rules both in RTL lint tool (like spyglass) and ATPG tool like Tessent, TK, TetraMax

Working experience in Genus, Synopsys TetraMax/DFTMax and Cadence Encounter Test is a plus

Ability to work in an international team, dynamic environment

Ability to learn and adapt to new tools and methodologies

Ability to do multi-tasking work on several high priority designs in parallel

Excellent problem solving skills

Excellent communication and team work skills and good English is required