Senior Debug Validation Engineer
Graphcore · Bengaluru
- Experience3–6 yrs
- SalaryNot disclosed
- Work modeunknown
- Levelmid
- Posted12 Sept 2026
About Graphcore
Graphcore is hiring in Bengaluru in semiconductors electronics. This role looks for around 3+ years of experience.
The role
Mid-level Debug Validation Engineer role at an AI compute hardware company, driving post-silicon debug and validation for next-generation AI compute silicon and systems. You will lead teams to identify, reproduce, analyse, and resolve complex silicon, firmware, and system-level issues, develop debug methodologies, and improve validation coverage and infrastructure using Python. Required skills include Python, C, Linux, SoC and platform architectures, scan, DFT, JTAG, trace infrastructure, fault tree analysis, failure isolation, fishbone methodologies, and system-level debug techniques; plus bare metal experience. Based in Bengaluru, Karnataka, India (work mode not specified).
Full job description
About Us
Graphcore is one of the world’s leading innovators in Artificial Intelligence compute.
It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry.
As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone.
Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation.
Job Summary
Reporting to senior leadership within Architecture and Validation, the Debug Validation Engineer will drive post-silicon debug and validation activities for next-generation AI compute silicon and systems. The role is responsible for leading teams focused on identifying, reproducing, analysing and resolving complex silicon, firmware and system-level issues during bring-up, characterization and product readiness.
This position combines deep technical debugging expertise with strong cross-functional collaboration across multiple engineering disciplines. The role will work closely with architecture, RTL, firmware, software and systems teams to improve debug methodologies, accelerate issue resolution and strengthen validation coverage. The role will work closely with architecture, RTL, firmware, software, systems and platform teams to improve debug methodologies, accelerate issue resolution and strengthen validation coverage.
The Team
The Post-Silicon Debug and Validation team sits within the Architecture and Validation organisation and is responsible for bring-up, debug and validation of Graphcore silicon and systems.
The team works across the full product lifecycle, supporting first silicon bring-up, subsystem validation, system integration and production readiness activities. Engineers collaborate closely with hardware, firmware, software and systems teams to investigate complex failures, develop debug methodologies and improve validation infrastructure.
Responsibilities and Duties
Lead post-silicon debug and validation activities for AI compute silicon and platform technologiesContribute to debug and validation activities across multiple projects and milestonesDrive prioritisation, planning and execution of debug and validation activities across multiple projects and milestonesInvestigate and resolve complex silicon, firmware, software and system-level issues during bring-up and validationDevelop structured debug methodologies and failure analysis processes to improve issue resolution efficiencyCollaborate closely with architecture, RTL, firmware, software and systems engineering teams to identify root causes and implement corrective actionsDrive debug of CPU, memory, interconnect and high-speed I/O subsystems under functional, stress and workload conditionsDevelop and enhance automated debug, regression and validation infrastructure using Python and related technologiesAnalyse logs, traces, telemetry and hardware data to isolate and characterize system failures and performance issuesSupport development of validation tests, debug tooling and custom diagnostics to improve coverage and observabilityDefine validation metrics, debug workflows and reporting standards to ensure consistent and repeatable analysisDrive continuous improvement of debug processes, validation methodologies and engineering workflowsCommunicate technical risks, status and recommendations clearly to engineering leadership and cross-functional stakeholdersSupport silicon readiness reviews and contribute to product quality and release decisionsContribute to continuous improvement of debug methodologies, validation infrastructure and engineering workflows
Candidate Profile
Essential
Strong experience in bare metal environmentsGood knowledge of SoC and platform architecturesExpertise in debug infrastructure and post-silicon debug methodologiesStrong programming skills in Python, C, or debug scripting languages such as CMMHighly motivated self-starter with a collaborative and team-oriented approachAbility to work across teams and programming languages to identify root causes of deep and complex issuesExperience of the post-silicon validation process applied in digital ASIC environmentsStrong Linux and Python experienceExceptional communication skills and the ability to collaborate effectively to solve complex problemsExcellent problem-solving, analytical and diagnostic skillsDeep knowledge of scan, DFT, JTAG and trace infrastructureStrong debug skills including fault tree analysis, failure isolation, fishbone methodologies and system-level debug techniquesAbility to work independently on technically complex debug and validation activities across hardware, firmware and software domains
Desirable
Understanding of DFT flows from insertion through post-silicon validationExperience developing tooling for parsing and analysing debug data, including scan dump parsingDriver-level experience with one or more of the following technologies:PCIeEthernetMemory technologies including LPDDR, DDR and HBMPeripheral interfaces such as I2C, I3C and SPIExperience using CoreSight and similar debug infrastructure including CTI, ETx, DStream, JLink, Lauterbach, ATB and STMGood knowledge of mixed-signal building blocks such as PLLs, high-speed PHYs and IC control/communication protocolsExperience with Arm CPU architectures, system IP and associated debug toolingExperience with AMBA protocolsUnderstanding of ML applications and associated workloadsExperience in characterization, failure analysis, test development, statistical analysis and customer support