RTL Design(Turing) -Sr Lead

Qualcomm · Bengaluru

  • Experience7–12 yrs
  • SalaryNot disclosed
  • Work modeonsite
  • Posted23 Sept 2026
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About Qualcomm

Qualcomm is hiring in Bengaluru in semiconductors electronics. This role looks for around 7+ years of experience.

Skills

  • RTL design
  • microarchitecture
  • Verilog
  • SystemVerilog
  • SoC integration
  • simulation debugging
  • Lint
  • CDC
  • formal verification
  • UPF
  • assertion-based verification
  • computer architecture
  • NoC design
  • low-power design
  • timing constraints
  • logic design
  • synthesis

The role

A design engineer at a semiconductor product company defines RTL microarchitecture and develops Verilog for high-performance AI/ML systems, ensuring low-power SoC integration through NoC design and formal verification.

Full job description

General Summary:

In this role

You will be interacting closely with the product definition and architecture team.

Developing implementation (microarchitecture and coding) strategies to meet quality, and PPAS (Performance Power Area Schedule) goals for Sub-system.

Define various aspects of the block level design such as block diagram, interfaces, clocking, transaction flow, pipeline, low power etc.

Perform as well as lead a team of engineers on RTL coding for Sub-system/SOC integration, function/performance simulation debug.

Drive Lint/CDC/FV/UPF checks to ensure design quality.

Develop Assertions as part of white-box testing-coverage.

Work with stakeholders to discuss the right collateral quality and identify solutions/workarounds.

Work towards delivering with key design collaterals (timing constraints, UPF etc.).

Desired Skillset:

Good understanding of low power microarchitecture techniques and AI/ML systems.

Thorough knowledge of Computer system architecture, including design aspects of AI/ML designs.

Experience in high performance design techniques and trade-offs in a Computer microarchitecture.

Good understanding of principals of NoC Design

Define Performance (Bandwidth, Latency) and Bus transactions sizing based on usecases across Voltage/Frequency corners

Working with Power and Synthesis teams on usecases, dynamic power and datapath interactions

Knowledge of Verilog / System Verilog. Experience with simulators and waveform debugging tools

Working with SOC DFT and PD teams as part of collaterals exchanges

Knowledge of logic design principles along with timing and power implications.

Preferred Qualifications:

Master's or Bachelor's degree in Electronics or Electrical Engineering or equivalent.

At least 7+ years of experience working on multiple designs.

Minimum Qualifications:

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.