RTL Design Engineer
AMD · Bengaluru
- Experience7–8 yrs
- SalaryNot disclosed
- Work modeonsite
- Levelexecutive
- Posted18 Sept 2026
About AMD
AMD is hiring in Bengaluru in semiconductors electronics. This role looks for around 7+ years of experience.
Skills
- Verilog
- SystemVerilog
- ASIC design
- digital design
- microarchitecture
- ASIC design quality flows
- Lint
- CDC
- RDC
- timing constraints
- synthesis
- low power design techniques
- UPF
The role
A digital design engineer at a semiconductor company microarchitects and implements ASIC components using Verilog, SystemVerilog, and cache coherency practices, while applying power management and timing closure. The role also uses low power design techniques and UPF.
Full job description
ADVANCE YOUR CAREER. ADVANCE THE WORLD.
At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.
Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.
RTL DESIGN ENGINEER
The Role
The focus of this role is to microarchitect , design and deliver data fabric IP RTL . These include new and existing features and components for AMD’s data fabric IP , working in close coordination with verification to ensure design quality.
THE PERSON:
You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
KEY RESPONSIBILITIES:
Digital design implementation and micro-architecture of components of the Infinity Data FabricMicro-architecture and RTL coding in Verilog/SystemVerilog of Data fabric components and its features as the fabric scales for server, data centre application systems.Design of Power Management flows and architecture for the fabric Collaborate with architectss to understand the new features to be implementeKnowledge of cache coherency and/or fabric /NOC design is a plusLeaf level cache designingCollaborating with verification and integration teams to resolve inter IP integration issuesDesign flow quality checks - Lint, CDC, RDC and othersTiming closure - timing constraints, synthesis, logic-depth reduction Design area optimizationsLow power design techniques, UPF included
PREFERRED EXPERIENCE:
7+ years of working experience in ASIC designProficiency in Verilog/SystemVerilog RTLExperience in full IP design cycle, requirements definition, architecture and microarchitecture specification.Active knowledge of ASIC design quality flows
ACADEMIC CREDENTIALS:
Bachelors or Masters degree in computer engineering/Electrical Engineering
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.