Principle DFT Engineer
NXP Semiconductors · Bengaluru
- Experience7–12 yrs
- SalaryNot disclosed
- Work modeunknown
- Levelexecutive
- Posted24 Sept 2026
About NXP Semiconductors
NXP Semiconductors is hiring in Bengaluru in semiconductors electronics. This role looks for around 7+ years of experience.
The role
Senior DFT Engineer role at a semiconductor manufacturing company (NXP Semiconductors) in Bengaluru, India, working on complex SoC test engineering across scan insertion, ATPG pattern generation/analysis, and gate-level simulation (GLS) with and without SDF. You will implement and verify scan architectures, generate and analyze ATPG patterns for stuck-at and transition faults, and execute GLS including SDF-based DFT validation. Required skills include Scan Insertion, ATPG, Gate-Level Simulation (GLS), stuck-at and transition fault testing, Verilog/SystemVerilog, and proficiency with Mentor/Siemens Tessent, Synopsys, or Cadence DFT tools. Work mode is not specified in the posting.
Full job description
We are seeking an experienced DFT Engineer (7–12 years) with strong hands-on expertise in Scan Insertion, ATPG, and Gate-Level Simulation (GLS) for complex SoC designs. The candidate will be responsible for implementing and verifying scan architectures, performing scan insertion, generating and analyzing ATPG patterns for stuck-at and transition faults, and executing GLS with and without SDF for DFT validation. The role requires close collaboration with RTL, physical design, and test teams to ensure high fault coverage, clean DFT signoff, and timely tape-out support. Proficiency with industry-standard DFT tools (Mentor/Siemens Tessent, Synopsys, or Cadence), solid Verilog/SystemVerilog skills, and the ability to debug DFT and GLS issues independently are essential. Prior experience supporting pre- and post-silicon activities is a plus.
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