Principal SoC Physical Implementation/STA Engineer
NXP Semiconductors · Bengaluru
- Experience12+ yrs
- SalaryNot disclosed
- Work modeunknown
- Levelstaff
- Posted19 Sept 2026
About NXP Semiconductors
NXP Semiconductors is hiring in Bengaluru in semiconductors electronics. This role looks for around 12+ years of experience.
The role
A staff-level Principal SoC Physical Implementation/STA Engineer role at semiconductor manufacturing company NXP Semiconductors, with 12+ years of Static Timing Analysis (STA) leadership for SoCs and blocks. You lead Synopsys Design Constraints (SDC) development (false paths and multicycle paths), perform MCMM timing signoff across PVT corners, debug setup/hold/transition and path-based violations (PBA), and drive timing closure via timing Engineering Change Orders (ECOs). You also automate timing flows and support script-based automation in Electronic Design Automation (EDA) tools, and debug timing issues from GLS/GDrive while guiding a team of STA engineers. Location is Bengaluru, Karnataka, India; work mode is not specified.
Full job description
Job Qualification
Experienced Static Timing Analysis (STA) Lead with 12+ years of experience doing STA for SoCs and Blocks.He/She should have experience of Multi mode timing constraint development, execution, and final timing signoff for advanced technology nodes.He/She will work closely with Architects,Front End,DFT and the PD team to understand design,clocking,timing ,Requirements and lead the writing constraints and closing timing activities
Key Responsibilities
Constraint Development: Create, validate, and maintain Synopsys Design Constraints (SDC) for block and full-chip levels, covering false paths, multicycle paths, and test modes.Timing Signoff: Perform exhaustive timing analysis across multiple corners and modes (MCMM), adhering to process, voltage, and temperature (PVT) variations.Violation Debugging: Debug and resolve setup, hold, transition, and path-based violations (PBA).Optimization & ECO: Drive timing closure by generating and evaluating timing Engineering Change Orders (ECOs).Cross-functional Collaboration: Partner with RTL, physical design, and DFT teams to ensure robust timing integration and refine timing models.Tool & Flow Automation: Develop and support implementation flows using industry-standard Electronic Design Automation (EDA) tools and improve script-based automation.Debugging timing issues from GLSDrive a team of STA engineers.
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