Principal Digital Design Engineer

NXP Semiconductors · Bengaluru

  • Experience10+ yrs
  • SalaryNot disclosed
  • Work modeunknown
  • Levelstaff
  • Posted11 Sept 2026
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About NXP Semiconductors

NXP Semiconductors is hiring in Bengaluru in semiconductors electronics. This role looks for around 10+ years of experience.

The role

Staff-level principal digital design engineer role at a semiconductor manufacturing company designing and optimizing digital logic circuits and systems across the full ASIC/FPGA design cycle. You will write RTL in Verilog/SystemVerilog/VHDL, build simulation-based functional verification and UVM/OVM testbenches, run synthesis and Static Timing Analysis with Design Compiler/Genus and PrimeTime, and debug at RTL, gate, and silicon using ModelSim, VCS, Xcelium, Verdi, and SimVision while targeting PPA (power, performance, area). Required skills include RTL design, FSMs, pipelining, clock domain crossing (CDC), low-power design techniques, and bus protocols (AXI, AHB, APB), plus FPGA/ASIC design flow and DFT concepts; experience with Python, Perl, or TCL is preferred. Based in Bengaluru, Karnataka, India (work mode not stated).

Full job description

An experienced Digital Design Engineer is responsible for designing, developing, and optimizing digital logic circuits and systems for semiconductor, FPGA, or ASIC-based products. The role involves working across the full design cycle—from specification and RTL design to verification, synthesis, and silicon validation.

Key Responsibilities

Design and develop RTL (Register Transfer Level) code using Verilog/SystemVerilog/VHDLArchitect and implement complex digital blocks and subsystemsPerform functional verification using simulation tools and methodologies (UVM/OVM)Develop and execute testbenches and validation plansPerform logic synthesis, timing analysis, and area optimizationDebug and troubleshoot design issues at RTL, gate, and silicon levelsCollaborate with verification, physical design, and firmware teamsEnsure designs meet power, performance, and area (PPA) targetsParticipate in design reviews, code reviews, and technical discussionsWork with EDA tools for design implementation and validationSupport post-silicon validation and bring-up activities

Technical Skills

Required Skills & Expertise

Strong proficiency in:Verilog / SystemVerilog / VHDLExperience with:RTL design and simulation tools (ModelSim, VCS, Xcelium)Synthesis tools (Design Compiler, Genus)Static Timing Analysis (PrimeTime)Understanding of:Digital logic design conceptsFSMs, pipelining, clock domain crossing (CDC)Low-power design techniquesKnowledge of:FPGA/ASIC design flowBus protocols (AXI, AHB, APB)Experience in debugging using:Waveform tools (Verdi, SimVision)

Preferred Skills

Experience with UVM-based verification methodologyFamiliarity with DFT (Design for Testability) conceptsExposure to scripting languages like Python, Perl, or TCLKnowledge of hardware-software co-designExperience in high-speed interfaces or SoC design

Experience Requirements

Typically 10+ years of experience in digital design or ASIC/FPGA developmentProven track record of successful tape-outs or product deliveries

Education

Bachelor’s or Master’s degree in:Electronics EngineeringElectrical EngineeringVLSI DesignComputer Engineering

Soft Skills

Strong problem-solving and debugging abilitiesExcellent communication and teamwork skillsAbility to work in fast-paced, deadline-driven environmentsAttention to detail and quality-focused mindset

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