Physical Design , Principal Engineer/Director, (Custom Silicon Group)

Qualcomm · Bengaluru

  • Experience17–25 yrs
  • SalaryNot disclosed
  • Work modeonsite
  • Posted23 Sept 2026
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About Qualcomm

Qualcomm is hiring in Bengaluru in semiconductors electronics. This role looks for around 17+ years of experience.

Skills

  • ASIC design
  • SoC design
  • physical design
  • floor planning
  • place-and-route
  • clock tree synthesis
  • static timing analysis
  • power analysis
  • low power verification
  • physical verification
  • timing closure
  • tapeout
  • signal integrity
  • design for manufacturability
  • Hardware Engineering
  • VLSI Engineering

The role

A physical design engineer at a semiconductor company leads ASIC development and delivers high-performance SoCs through physical design, timing signoff, and tapeout. The role applies floor planning, place-and-route, and static timing analysis while guiding cross-functional engineering teams and customer silicon solutions.

Full job description

General Summary

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next generation experiences and drives digital transformation to help create a smarter, connected future for all. As an ASIC Design Manager (Principal / Director-Level) in the Custom Silicon Group, you will lead the development and delivery of next-generation, high-performance SoCs from concept to tapeout. You will be responsible for driving the complete silicon development lifecycle, spanning architecture, RTL design, integration, physical design, verification, silicon bring-up, and production readiness. In addition to providing technical and organizational leadership, you will serve as a key customer-facing engineering leader, partnering with strategic customers and stakeholders to translate business requirements into successful silicon solutions.

You will lead a team of engineers and work closely with cross-functional groups across geographies - including RTL design, verification, CAD, and integration teams. Your role will be pivotal in shaping the physical design strategy, ensuring design convergence, and maintaining signoff integrity across timing, power, and area metrics.

Minimum Qualifications

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience.

OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience.

OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.

Principal Duties and Responsibilities

Demonstrate proven experience in executing responsibilities across multiple sites.

Lead and manage a team across multiple functions.

Design closure and tapeout expertise in advanced technology nodes.

Complete ownership of PnR implementation, including Floor planning, Placement, CTS, and post-route activities on the cutting-edge nodes.

Possess mandatory signoff knowledge, including STA, Power Analysis, FV, Low Power Verification and PV.

Collaborate effectively to resolve issues related to constraints validation, verification, STA, Physical Design and tapeout.

Understand deep sub-micron design challenges, including leakage power, signal integrity, and DFM.

Support pre-sales and business development activities by evaluating technical feasibility and providing design expertise.

Provide technical leadership during design reviews and executive-level customer engagements.

Drive resolution of customer-reported issues by coordinating across design, verification, firmware, software, and validation teams.

Minimum Qualifications

Bachelor's or Masters degree in Electrical/Electronics Engineering and 17- 25 years of Hardware/VLSI Engineering specializing in Physical Design and timing signoff for high-speed SoCs.

Preferred Qualifications

Excellent hands-on experience on Floor planning, PnR and STA flows

Good knowledge of Placement/Clock Tree Synthesis (CTS), Low Power/High Performance optimization etc.

Thorough understanding of signoff domains LEC/CLP/PDN etc.

18+ years of experience with Physical Design and timing signoff expertise in latest tech nodes (e.g., 2nm/3nm/4nm/5nm)